The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.

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