To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.

To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes / The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls

This master´s thesis deals with QFN packages soldering and technology procedures optimization. The aim of theoretical part is description of QFN packages, their assembly and reflow soldering on PCB in HONEYWELL. The aim of the practical part is to propose a method of measuring temperature and optimizing the thermal profiles of selected PCB with QFN packages by using convection (HONEYWELL) and infrared (BUT) reflow ovens. Comparison and evaluation of thermal profiles for 3 production PCBś with QFN packages using solder paste AIM NC257-2 were realised. The main part of master´s thesis are appearance evaluation of solder joints, preparing microsection and measuring intermetallic layers thickness by using the optical and the scanning electron microscopes, analysation and study of QFN defects created during soldering proces. These tests were performed with 2 production PCB´s. Optimization of SPI and soldering technology procedures where were analyzed QFN packages were processed on one type of PCB. Interesting part of this diplomma thesis is creating of the 3D heat transfer model of QFN package during the reflow soldering in SolidWorks.

The topic of this dissertation is the derivation, development, and evaluation of novel hybrid algorithms for process control that use a limited number of measurements and that are suitable to operate in the presence of large amounts of process noise. As an initial step, affine and neural network statistical process models are developed in order to simulate the steady-state system behavior. Such models are vitally important in the evaluation, testing, and improvement of all other process controllers referred to in this work. Afterwards, fuzzy logic controller rules are assimilated into a mathematical characterization of a model that includes the modes and mode transition rules that define a hybrid hierarchical process control. The main processing entity in such framework is a closed-loop control algorithm that performs global and then local optimizations in order to asymptotically reach minimum bias error; this is done while requiring a minimum number of iterations in order to promptly reach a desired operational window. The results of this research are applied to surface mount technology manufacturing-lines yield optimization. This work achieves a practical degree of control over the solder-paste volume deposition in the Stencil Printing Process (SPP). Results show that it is possible to change the operating point of the process by modifying certain machine parameters and even compensate for the difference in height due to change in print direction.