Digitally-controlled, high power universal telecommunication power supply modules have been developed. In this work, the converter control strategy, and its design and implementation first, by means of parallel-operated, dual, 8-bit microcontrollers, and then by using a high processing power digital signal processor (DSP) have been emphasized. The proposed dual-processor based digital controller provides an extended operating output voltage range of the power supplies, user programmable current limit setting, serial communication based active load current sharing with automatic master-slave selection among parallel-operated modules, user selectable number of back-up battery cells, programmable temperature compensation curves, and automatic derating without extra hardware requirement. Overload and output short-circuit protection features are also controlled by software. One of the processors in the digital controller is employed for user interface purposes such as long term records, display, and alarm facilities, and remote control, which are inherently slow processes. The fast processing speed required by output voltage setting, current limit, and load current sharing however is to be fulfilled by a second processor dedicated to the adjustment of output voltages of modules. Tight dynamic load regulation requirement of a telecommunication power supply has been fulfilled by a 150 MIPS DSP, in place of a low cost, 8-bit microcontroller. The implemented digitally-controlled, 1.8 kW, 0-70V telecommunication power supplies have been tested successfully in several locations in the field.

abstract: To establish reliable wireless communication links it is critical to devise schemes to mitigate the effects of the fading channel. In this regard, this dissertation analyzes two types of systems: point-to-point, and multiuser systems. For point-to-point systems with multiple antennas, switch and stay diversity combining offers a substantial complexity reduction for a modest loss in performance as compared to systems that implement selection diversity. For the first time, the design and performance of space-time coded multiple antenna systems that employ switch and stay combining at the receiver is considered. Novel switching algorithms are proposed and upper bounds on the pairwise error probability are derived for different assumptions on channel availability at the receiver. It is proved that full spatial diversity is achieved when the optimal switching threshold is used. Power distribution between training and data codewords is optimized to minimize the loss suffered due to channel estimation error. Further, code design criteria are developed for differential systems. Also, for the special case of two transmit antennas, new codes are designed for the differential scheme. These proposed codes are shown to perform significantly better than existing codes. For multiuser systems, unlike the models analyzed in literature, multiuser diversity is studied when the number of users in the system is random. The error rate is proved to be a completely monotone function of the number of users, while the throughput is shown to have a completely monotone derivative. Using this it is shown that randomization of the number of users always leads to deterioration of performance. Further, using Laplace transform ordering of random variables, a method for comparison of system performance for different user distributions is provided. For Poisson users, the error rates of the fixed and random number of users are shown to asymptotically approach each other for large average number of users. In contrast, for a finite average number of users and high SNR, it is found that randomization of the number of users deteriorates performance significantly. / Dissertation/Thesis / Ph.D. Electrical Engineering 2010

Asset management and automation are acknowledged by distribution utilities as a useful strategy to improve service quality and reliability. However, the major challenge faced by decision makers in distribution utilities is how to achieve long-term return on the projects while minimising investment and operation costs. Distribution automation (DA) in terms of transformer economic operation (TEO), distribution network reconfiguration (DNR), and sectionalising switch placement (SSP) is recognised as the most effective way for distribution network operators (DNOs) to increase operation efficiency and reliability. Automated tie-switches and sectionalising switches play a fundamental role in distribution networks. A method based on the Monte Carlo simulation is discussed for transformer loss reduction, which comprises of profile generators of residential demand and a distribution network model. The ant colony optimisation (ACO) algorithm is then developed for optimal DNR and TEO to minimise network loss. An ACO algorithm based on a fuzzy multi-objective approach is proposed to solve SSP problem, which considers reliability indices and switch costs. Finally, a multi-objective ant colony optimisation (MOACO) and an artificial immune systems-ant colony optimisation (AIS-ACO) algorithm are developed to solve the reconfiguration problem, which is formulated within a multi-objective framework using the concept of Pareto optimality. The performance of the optimisation techniques has been assessed and illustrated by various case studies on three distribution networks. The obtained optimum network configurations indicate the effectiveness of the proposed methods for optimal DA.

No description available.

O projeto e o desenvolvimento de circuitos integrados é um dos mais importantes e aquecidos segmentos da indústria eletrônica da atualidade. Neste cenário, ferramentas de automação têm possibilitado aos projetistas manipular uma elevada quantidade de transistores em circuitos cada vez mais complexos, diminuindo, assim, o tempo de projeto. Em especial, ferramentas de síntese lógica têm contribuído significativamente para reduzir o ciclo de desenvolvimento. Na metodologia de projeto full-custom, cada bloco funcional tem sua geração realizada de forma manual, desde a implementação das redes de transistores até a geração do leiaute. Entretanto, esta tarefa é extremamente custosa em tempo de projeto. Neste contexto, torna-se confortável ter a disposição algoritmos dedicados para derivar redes de transistores automaticamente. Diversos tipos de arranjos de transistores são encontrados na literatura. Estas diferentes redes de transistores apresentam diferentes comportamentos em termos de consumo de área, consumo de potência e velocidade. Desta forma, não apenas a geração automática de redes de transistores é importante, mas também técnicas automatizadas para avaliar e comparar estas distintas redes de chaves é de fundamental importância para guiar o projetista que deseja alcançar implementações de circuitos eficientes. Estas avaliações não precisam ser necessariamente processos custosos de caracterização elétrica. Elas podem ser realizadas através de estimativas capazes de fornecer informações acuradas sobre o comportamento das redes. Esta idéia pode ser utilizada por projetistas que desejam gerar e avaliar potenciais soluções em redes de transistores para alimentar fluxos standard-cell (utilizando bibliotecas de células), ou por aqueles que utilizam a abordagem de mapeamento tecnológico library-free (fazendo uso de geradores de células). Neste contexto, este trabalho apresenta um gerador automático de redes de transistores capaz de fornecer diferentes tipos de redes em diversos estilos lógicos. Para comparar as redes geradas, algumas técnicas de estimativa são empregadas. Comparações são realizadas sobre conjuntos distintos de funções Booleanas, demonstrando as vantagens da utilização de lógicas alternativas em relação ao difundido padrão CMOS. / Currently, VLSI design has established a dominant role in the electronics industry. Automated tools have enabled designers to manipulate more transistors on a design project and shorten the design cycle. In particular, logic synthesis tools have contributed significantly to reduce the design cycle time. In full-custom designs, manual generation of transistor netlists for each functional block is performed, but this is an extremely time-consuming task. In this sense, it becomes comfortable to have efficient algorithms to derive transistor networks automatically. There are several kinds of transistor networks arrangements. These different networks present different behaviors in terms of area, delay and power consumption. Thus, not only automatic transistor networks generation is important, but also an automated technique to evaluate and to compare the distinct switch networks is fundamental to guide designers that need to achieve efficient circuit implementations. This evaluation not necessarily needs to be an expensive electrical characterization process. It can be obtained through estimation processes capable of delivering good information about the logic cells behavior. This idea is useful for those designers that desire to generate and to evaluate potential transistor network implementations to feed standard-cell flow designs (using cell libraries), or for those designers who target the use of library-free technology mapping concept (using automatic cells generators). In this context, this work presents an automated transistor network generator able to delivery different kinds of networks in several logic styles. In order to compare the obtained networks, some estimation techniques are employed. A comparison is done over a set of Boolean function benchmarks, showing the advantages of using alternative logic styles over the traditional Complementary Series-Parallel CMOS (CSP CMOS).

abstract: Programmable metallization cell (PMC) technology employs the mechanisms of metal ion transport in solid electrolytes (SE) and electrochemical redox reactions in order to form metallic electrodeposits. When a positive bias is applied to an anode opposite to a cathode, atoms at the anode are oxidized to ions and dissolve into the SE. Under the influence of the electric field, the ions move to the cathode and become reduced to form the electrodeposits. These electrodeposits are filamentary in nature and persistent, and since they are metallic can alter the physical characteristics of the material on which they are formed. PMCs can be used as next generation memories, radio frequency (RF) switches and physical unclonable functions (PUFs). The morphology of the filaments is impacted by the biasing conditions. Under a relatively high applied electric field, they form as dendritic elements with a low fractal dimension (FD), whereas a low electric field leads to high FD features. Ion depletion effects in the SE due to low ion diffusivity/mobility also influences the morphology by limiting the ion supply into the growing electrodeposit. Ion transport in SE is due to hopping transitions driven by drift and diffusion force. A physical model of ion hopping with Brownian motion has been proposed, in which the ion transitions are random when time window is larger than characteristic time. The random growth process of filaments in PMC adds entropy to the electrodeposition, which leads to random features in the dendritic patterns. Such patterns has extremely high information capacity due to the fractal nature of the electrodeposits. In this project, lateral-growth PMCs were fabricated, whose LRS resistance is less than 10Ω, which can be used as RF switches. Also, an array of radial-growth PMCs was fabricated, on which multiple dendrites, all with different shapes, could be grown simultaneously. Those patterns can be used as secure keys in PUFs and authentication can be performed by optical scanning. A kinetic Monte Carlo (KMC) model is developed to simulate the ion transportation in SE under electric field. The simulation results matched experimental data well that validated the ion hopping model. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

Une nouvelle famille de porphyrines chirales bridées a été mise au point dans le but d'accéder à des systèmes présentant un processus redox irréversible, lié à une bistabilité conformationnelle, dans le but de les appliquer dans le domaine des mémoires moléculaires. Ces nouvelles porphyrines sont constituées de deux brides ancrées sur les quatre positions meso par des groupes cyclohexyle. Une amine secondaire a été insérée au centre des brides dans le but d'obtenir des métalloporphyrines présentant une seule conformation à l'équilibre pour une longueur de bride, un métal et un degré d'oxydation donnés et pour favoriser un changement conformationnel en fonction du degré d'oxydation d'un métal comme le manganèse. Pour cela, une nouvelle voie de synthèse des porphyrines bridées par pré-fonctionnalisation du dialdéhyde autour de la fonction amine a été conçue. Les porphyrines ont été caractérisées par spectroscopie RMN, spectroscopie UV-Visible et dichroïsme circulaire. Les conformations des bases libres, des complexes de zinc(II) et de nickel(II) ont été déterminées par RMN proton. Pour une longueur de bride de 9 atomes avec une amine secondaire, les conformations des complexes de zinc(II) et de nickel(II) sont respectivement αααα et ααββ. En partant de ce modèle, les complexes de manganèse(II) et de chloromanganèse(III) ont été synthétisés et caractérisés par spectroscopie UV-Visible, dichroïsme circulaire et RMN du carbone 13 afin d'étudier si des changements de conformation en fonction du degré d'oxydation du métal ont lieu. / A new family of chiral bridled porphyrins was designed in order to access systems presenting an irreversible redox process linked to a conformational switch. Such systems could be of high interest in the field of molecular memories. These new porphyrins are made of two bridles anchored to the four macrocycle meso positions through cyclohexyl groups. The first objective is to introduce a secondary amine in the centre of the bridles in order to allow metalloporphyrins with defined bridle length and specific metal with a given oxidation degree to be only under one conformation at equilibrium. The second objective is to favor a conformational switch dependent on the oxidation state of a redox metal such as manganese. To reach these goals, a new porphyrin synthetic pathway was established. The key steps of this new protocol were the synthesis of the bridle built around the central amine with two terminal aldehyde functions required for the macrocyle formation. Porphyrins were studied by NMR, UV-Visible and circular dichroism spectroscopies. The conformations of free base porphyrins, zinc(II) complexes and nickel(II) complexes were determined by 1H NMR. For a bridle with a chain length of 9 atoms including the secondary amine, the zinc(II) complex presents only an αααα conformation and nickel(II) complex an ααββ conformation. From these structural models, manganese(II) and chloromanganese(III) complexes were synthesised and characterised by UV-Visible spectroscopy, circular dichroism and 13C NMR in order to study the possible conformational switches dependent on the Mn redox state.

Cette thèse s'inscrit dans la continuité des études menées pour améliorer la fiabilité des relais MEMS ohmiques et comprendre les mécanismes de dégradation se produisant au niveau du contact électrique aux échelles micro et sub-micrométriques. Les deux premiers chapitres de ce manuscrit permettent d'établir l'état de l'art du domaine et de décrire les différentes techniques expérimentales utilisées afin de caractériser les mécanismes physiques se produisant lors de l'ouverture et la fermeture d'un relais MEMS sous courant. Le troisième chapitre étudie qualitativement et quantitativement le transfert de matière aux distances sub-micrométriques. L'utilisation d'un microscope à force atomique (AFM) permet d'identifier les paramètres clés, notamment la tension de contact à l'état ouvert et la vitesse de commutation. L'origine de ce transfert de matière est attribuée à des émissions de courant se produisant dans les derniers nanomètres avant la fermeture du contact. Un plasma métallique est également observé et caractérisé pendant les phases de commutations. Ces observations conduisent à l'élaboration d'un scénario permettant d'expliquer le transfert de matière à ces dimensions. Le quatrième chapitre se consacre en première partie à l'étude des rebonds lors de la fermeture du contact. On montre que des rebonds peuvent apparaître quelques µs après la fermeture du contact au cours des cycles. Ceux-ci semblent être des indicateurs de la fin de vie du composant. D'autres rebonds, liés aux forces électrostatiques de contact, sont également mis en évidence lors de fermetures à faibles vitesses (qq nm/s). L'importance de ces forces est néanmoins du second ordre et ces derniers rebonds n'interviennent pas directement dans la phase de fermeture d'un relais MEMS. L'étude de la quantification de la résistance de contact lors de l'ouverture du contact constitue la deuxième partie de ce dernier chapitre. La nature quantique de ce phénomène est mise en évidence dans deux dispositifs : un interrupteur MEMS et à l'aide d'un AFM. Il est notamment montré que ce phénomène est seulement observable pour des courants inférieurs à 100µA. Finalement, l'ensemble de ces travaux mènent à différentes recommandations, détaillées en conclusion, nécessaires pour assurer le bon fonctionnement des relais MEMS. / This thesis aims to improve the reliability of ohmic MEMS switches and focuses on the degradation mechanisms of the electrical contact at the micro and nano-scales. The two first chapters of the manuscript provide a state-of–the-art of MEMS switches and describe the different experimental techniques used to characterize the physical phenomena involved in the opening and closure of a MEMS switch under current (“hot switching actuation”). The third chapter studies qualitatively and quantitatively the material transfer at sub micrometer scale. An Atomic Force Microscope (AFM) is used to identify the main parameters involved in this phenomenon such as the opening contact voltage and the closing velocity. The origin of the material transfer is attributed to field emission in the last tens of nanometers before the contact closure. A metallic plasma is also observed and characterized during switching operations. According to the different observations, a scenario is suggested to explain material transfer at such small dimensions. The fourth chapter deals with dynamic observation during switching operations. First, bounces can be detected after a few millions of operations, they usually appear a few µs just after the first contact. Such bounces seem to be an early indicator of the lifetime of those devices. Other types of bounces related to the electrostatic contact force can be observed at very low closing velocity (a few nm/s). Nevertheless in a MEMS switch the closing and opening velocity is high enough to avoid such bounces. The second part of this chapter investigates the contact conductance quantization during the opening phase of a contact. We show that this phenomenon can be observed in a MEMS switch and with an AFM when the current is lower than 100µA. As a conclusion, several recommendations are provided to improve the reliability of MEMS switches.

Due, in part, to the nowadays considerable body of theoretical results for Markov Jump Linear Systems (MJLS), there has been recently an intense interplay between the classical switch systems and MJLS theory. Although the development of these theories came up independently, in a broad way MJLS can be seen as a class of switch systems with a stochastic switching mecanism. Motivated by the diversity of methods of these theories and its potentiality in the treatment of systems with requires tolerance to failure (the so-called safety-critical and highintegrity systems), it is our intention in this dissertation to make up a synthesis of the most relevant methods, setting against the two theories. In view of the huge amount of results of these theories, we focus here just on the stability problem. We begin presenting well known tools such as common Lyapunov functions and others which are related to involving classes of linear subsistems with certain particularities such as commutativity and solubility of Lie algebra. Rigth after, we present the concept of average dwell time, part Lyapunov functions and results about design of switch. Using the average dwell time at the linear systems with stable and unstable systems with the rules already demonstrated we claim some results about stability that applied at linear systems with markovian switch. / Devido em parte, ao considerável corpo de resultados teóricos para Sistemas Lineares com Saltos Markovianos (SLMS), tem havido recentemente uma intensa interação entre a teoria clássica de sistemas com chaveamento (switched systems) e a teoria de SLSM. Apesar do desenvolvimento dessas teorias terem acontecido essencialmente de maneira independentes, num sentido amplo SLMS pode ser visto como um sistema com chaveamento cujo mecanismo de chaveamento é estocástico. Motivados pela diversidade de métodos dessas teorias e sua enorme potencialidade no tratamento de sistemas que exigem comportamentos tolerantes a falhas (faz parte do que se denomina na literatura especializada como safety-critical and high integrity systems) é nossa intenção nesta dissertaçãoo fazer uma síntese dos métodos mais relevantes, contrapondo as duas teorias. Tendo em vista a enorme quantidade de resultados, focaremos apenas o problema de estabilidade. Começaremos o estudo com critérios já conhecidos como a construção de uma função comum de Lyapunov para os sistemas e outros que dizem respeito à estabilidade em classes de subsistemas lineares que possuem certas particularidades como comutatividade e solubilidade da álgebra de Lie gerada pela coleção de matrizes. Em seguida, apresentaremos os conceitos de tempo médio de habitação, funções de Lyapunov por partes e os resultados sobre design de switch. Através do estudo do tempo médio de habitação em sistemas lineares com matrizes estáveis e instáveis, juntamente com os critérios já estudados referentes às classes de subsistemas para as quais é possível a construção de uma função comum de Lyapunov, chegamos a alguns resultados para estabilidade, que aplicamos ao caso de chaveamento Markoviano.

O projeto e o desenvolvimento de circuitos integrados é um dos mais importantes e aquecidos segmentos da indústria eletrônica da atualidade. Neste cenário, ferramentas de automação têm possibilitado aos projetistas manipular uma elevada quantidade de transistores em circuitos cada vez mais complexos, diminuindo, assim, o tempo de projeto. Em especial, ferramentas de síntese lógica têm contribuído significativamente para reduzir o ciclo de desenvolvimento. Na metodologia de projeto full-custom, cada bloco funcional tem sua geração realizada de forma manual, desde a implementação das redes de transistores até a geração do leiaute. Entretanto, esta tarefa é extremamente custosa em tempo de projeto. Neste contexto, torna-se confortável ter a disposição algoritmos dedicados para derivar redes de transistores automaticamente. Diversos tipos de arranjos de transistores são encontrados na literatura. Estas diferentes redes de transistores apresentam diferentes comportamentos em termos de consumo de área, consumo de potência e velocidade. Desta forma, não apenas a geração automática de redes de transistores é importante, mas também técnicas automatizadas para avaliar e comparar estas distintas redes de chaves é de fundamental importância para guiar o projetista que deseja alcançar implementações de circuitos eficientes. Estas avaliações não precisam ser necessariamente processos custosos de caracterização elétrica. Elas podem ser realizadas através de estimativas capazes de fornecer informações acuradas sobre o comportamento das redes. Esta idéia pode ser utilizada por projetistas que desejam gerar e avaliar potenciais soluções em redes de transistores para alimentar fluxos standard-cell (utilizando bibliotecas de células), ou por aqueles que utilizam a abordagem de mapeamento tecnológico library-free (fazendo uso de geradores de células). Neste contexto, este trabalho apresenta um gerador automático de redes de transistores capaz de fornecer diferentes tipos de redes em diversos estilos lógicos. Para comparar as redes geradas, algumas técnicas de estimativa são empregadas. Comparações são realizadas sobre conjuntos distintos de funções Booleanas, demonstrando as vantagens da utilização de lógicas alternativas em relação ao difundido padrão CMOS. / Currently, VLSI design has established a dominant role in the electronics industry. Automated tools have enabled designers to manipulate more transistors on a design project and shorten the design cycle. In particular, logic synthesis tools have contributed significantly to reduce the design cycle time. In full-custom designs, manual generation of transistor netlists for each functional block is performed, but this is an extremely time-consuming task. In this sense, it becomes comfortable to have efficient algorithms to derive transistor networks automatically. There are several kinds of transistor networks arrangements. These different networks present different behaviors in terms of area, delay and power consumption. Thus, not only automatic transistor networks generation is important, but also an automated technique to evaluate and to compare the distinct switch networks is fundamental to guide designers that need to achieve efficient circuit implementations. This evaluation not necessarily needs to be an expensive electrical characterization process. It can be obtained through estimation processes capable of delivering good information about the logic cells behavior. This idea is useful for those designers that desire to generate and to evaluate potential transistor network implementations to feed standard-cell flow designs (using cell libraries), or for those designers who target the use of library-free technology mapping concept (using automatic cells generators). In this context, this work presents an automated transistor network generator able to delivery different kinds of networks in several logic styles. In order to compare the obtained networks, some estimation techniques are employed. A comparison is done over a set of Boolean function benchmarks, showing the advantages of using alternative logic styles over the traditional Complementary Series-Parallel CMOS (CSP CMOS).