In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.

In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator.

Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 76-77). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2004. / Printout. Includes bibliographical references (leaves 39-40). Also available on the World Wide Web.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (Ph. D.)--Ruhr Universität Bochum, 1983. / Vita.

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