Due to the continuous power supply reduction, Charge Pumps, also referred to as DC-DC converters, circuits are widely used in integrated circuits (ICs) to generate high voltages for many applications, such as EEP-ROMs, Flash memories for programming and erasing of the floating gate, switched capacitor circuits, operational amplifiers, voltage regulators, LCD drivers, piezoelectricactuators, etc. A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create either a higher or lower voltage power source. The development of the charge pumps is motivated by ever increasing the needs for the small form factor (i.e small size and low weight), high-conversion-efficiency and low costpower management system, which is the best candidate suitable to meet the needs of continuosly shrinking portable electronic devices like MP3 players, cellular phones, PDA's. / text

This thesis presents the design of new integrated charge pumps with high performance. An analysis method is determined to evaluate the voltage gain, the output resistance and the conversion efficiency parameters of integrated charge pumps. An optimization method is developed to improve the performance through capacitor sizing based on area constraints. Several charge pumps structures are optimized and compared including the losses due to devices parasitics. Results show that the Dickson charge pump (voltage doubler) is the best structure for integration. Therefore, techniques to improve per- formance and conversion efficiency of integrated voltage doubler are proposed. Switch bootstrapping technique prevents short-circuit losses, improves driving capability, and enhances the overall efficiency. The application of charge reuse technique reduces the dynamic power losses of integrated voltage doublers and double charge pumps. A pro- totype of the integrated voltage doublers was fabricated in a 0.18-μm CMOS process with the proposed techniques. Measured results have been presented, demonstrating the improvements in performance and conversion efficiency, with a good correlation between measured and predicted results.

This thesis presents the design and implementation of PMOS-based integrated charge pumps with extended voltage range and their regulation circuits in a standard process. The performance of charge pumps are evaluated by their output resistances and power conversion efficiencies. Formulas which describe the charge pump characteristics are developed and presented. Existing charge pumps are analyzed and studied to understand their limitations in generating high voltages and achieving high performance. The proposed charge pump structures are designed to use PMOS switches to alleviate the high voltage stresses across transistors by biasing their bulk independently. The voltages across transistors and capacitors are kept within the suggested voltage rating (VDD)regardless of how high the output voltage is, thus the maximum voltage range is extended and no longer limited by the breakdown voltages of the devices. The charge pump circuits only need low-voltage devices and standard processes, and can be easily integrated in a digital or mixed-signal design. The proposed charge pump regulation circuits include a voltage divider, a voltage controlled ring oscillator and a feedback operational amplifier. The regulation circuits are able to adjust the clock frequency to regulate the charge pump to a steady output voltage (set by the reference voltage) under a large range of current loads. A test chip including the proposed charge pumps and regulation circuits was fabricated in a 0.18 um digital CMOS process provided by Taiwan Semiconductor Manufacturing Company (TSMC). The proposed charge pumps were tested and demonstrated the reliable generation of output voltages up to 11.47 V using only low-voltage devices. The simulation and measurement results have been presented and compared, demonstrating the functionality and performance of the proposed circuits. / Kapik Integration, Mitacs

Indiana University-Purdue University Indianapolis (IUPUI) / With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed. The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages. The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of $25mV. FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.

In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369 pJ/conv-step, which is almost 40% lower than that of the conventional ADC.

In the present thesis, I have proposed methodology of two stages Dickson charge pump, which is capable of harvesting energy at 2.45 GHz RF signal to power any low powered device. Presented design uses a simple and inexpensive circuit consisting of four microstrip patch antennas, some zero-bias Schottky diodes, Wilkinson power divider and a few passive components. Circuit was fabricated on a 60 mils RO4350B substrate (=3.66), with 1.4 mils copper conductor. Demonstration showed the charge pump provides a good performance, as it drives the low powered devices with as low as 10dBm input power at 1m away from the energy source. Thesis paper will present design techniques illustrated with data obtained on prototype circuits. The objective is to wirelessly gather energy from one RF source and convert it into usable DC power that is further applied to a set of low power electronic devices. Radio Frequency Identification (RFID) tag system could also be improved using this method. RF-to-DC conversion is accomplished by designing and characterizing an element commonly known as a Rectenna, which consists of an antenna and an associated rectification circuitry. The rectenna is fully characterized in this dissertation and is used for charging low powered devices.

In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Different loop parameter specificationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. This thesis describes the implementation of a semi-digital PLLfor high bandwidth applications, which is self-compensated, low-power and exhibits band-width tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOStechnology.This design can be used for a wide range of reference frequencies without redesigning anyblock. The bandwidth can be fixed to some fraction of the reference frequency during designtime. In this thesis, the PLL is designed to make the bandwidth track 5% of the referencefrequency. Since this PLL is self-compensated, the PLL performance and the bandwidthremains same over PVT corners.