Master of Science / Department of Electrical and Computer Engineering / Dwight D. Day / Low-power systems implemented on Field Programmable Gate Arrays (FPGA) have become more practical with advancements leading to decreases in FPGA power consumption, physical size, and cost. In systems that may need to operate for an extended time independent of a central power source, low-power FPGA’s are now a reasonable option. Combined with research into energy harvesting solutions, a FPGA-based system could operate independently indefinitely and be cost effective. Four simple demodulator designs were implemented on a FPGA to test and compare the performance and power consumption of each. The demodulators were a Counter that tracked the length of the input signal period, a One-Shot that counted the input edges over time, a Phase-Frequency Detector (PFD), and a PFD with preprocessing on the input signal to mitigate distortion introduces by the 1-bit subsampling. The designs demodulated a binary frequency shift keying (BFSK) signal using 10.69MHz and 10.71MHz as the input frequencies and a 1kHz data rate. The signal was 1-bit subsampled at 75kHz to provide the demodulators with a signal containing 15kHz and 35kHz. The design size, power consumption, and error performance of each demodulator were compared. At the frequencies and data rate used, the Counter and One-Shot are the most energy efficient by a significant margin over the PFDs. The error performance was nearly equal for all four. As the BFSK baseband frequencies and especially the data rate are increased, the PFD options are expected to be the better options as the Counter and One-Shot may not react quickly enough.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

Das vorliegende Policy Paper fasst Beschreibungen und Einschätzungen der Partnerschaften für Demokratie (PfD) und der Träger der ebenfalls vom Bundesprogramm „Demokratie leben!“ geförderten Modellprojekte im Freistaat Sachsen auf Grundlage einer explorativen Befragung erstmals zusammen. In dieser Weise sollen in Zusammenarbeit mit dem Demokratie-Zentrum Sachsen (DZ) künftig regelmäßig demokratiegefährdende Entwicklungen und Herausforderungen für die Zivilgesellschaft und die kommunale Verwaltung, aber auch innovative Projekte und Erfolge landesweit erfasst werden. Das Gesamtbild der anonymisierten Antworten soll einerseits zum Diskussionsprozess unter den Trägern selbst beitragen. Andererseits sollen die Leistungen wie auch die Wahrnehmungen der PfD und Modellprojekte für die Zivilgesellschaft sowie die Landes- und Kommunalpolitik sichtbarer gemacht werden. Die Arbeit der PfD wie auch der Modellprojekte fußt auf einer engen Zusammenarbeit zwischen verschiedenen Akteuren aus Verwaltung und Zivilgesellschaft. Umso mehr können die gebündelte Expertise und das Vor-Ort-Wissen, wie es in diesem Bericht zusammengetragen wurde, zur Stärkung der demokratischen Zivilgesellschaft beitragen.

This thesis work is based on the previous researches in design automation at Sandvik Coromant. The concept of product family description (PFD) has been introduced to the company to improve documentation of knowledge in engineering design process. Current documentation at the company for engineering design covers mostly the design definition part of the knowledge. PFD is constituted by design definition and completed by design rationale. This kind of documentation improves reusing, revising and expanding the knowledge at the company. On the other side, PFD is an input for design programming and a good engineering design description for a product provides more efficiency in design programming. The project is started by a survey for several principles and applications for knowledge modelling. Product variant master (PVM) and Semantic MediaWiki are selected by the results of the survey. To show the concept of PVM, modelling of a test product is done in product model manager (PMM) software. The main part of the project is setting up product family description (PFD) by capturing design rationale for the test product, implementing in Semantic MediaWiki. Since the design rationale is not documented, it was recorded during several meetings with the designer of the test product. The description is completed by including the argumentations about the rules, figures, dimensions and etc. Also in the project has been tried to improve and revise the description to make it more simple and efficient. Another objective of the project is to show Semantic MediaWiki as a candidate application for modelling knowledge at the company. In this step the applicability and functionality of both PFD and Semantic MediaWiki is seen. In the next stage the project findings and company documentation are evaluated. In this step has been tried to show the pros and cons of the project. The emphasis of the evaluation is on PFD and the alternative application. In the end a conclusion of the whole methods and findings of the project comes with discussion with people who were involved in this work.

Bakgrund: Förlossningsskador kan ge fysiska och psykiska besvär. Skadorna är olika omfattande och eftervården är viktig för att rehabilitera kvinnan. Fysioterapeuters kompetens lämpar sig för undersökning och behandling av förlossningsskador. Dock är professionen inte en självklar del av eftervården och det finns kunskapsluckor om fysioterapeuters upplevelser och erfarenheter av att arbeta med förlossningsskador. Syfte: Syftet med den här studien var att beskriva fysioterapeuters upplevelser och erfarenheter inom den svenska sjukvården av att arbeta med kvinnor som har förlossningsskador. Metod: Studien var en semi-strukturerad kvalitativ intervjustudie som inkluderade fem deltagare som arbetar med förlossningsskador. Deltagarna rekryterades via Fysioterapeuternas hemsida på kompetenskartan för kvinnors hälsa och Facebookgruppen "Fysioterapeuter inom kvinnors hälsa”. Ändamålsenligt bekvämlighetsurval tillämpades. Databearbetning av intervjumaterialet gjordes genom en kvalitativ innehållsanalys. Resultat: Analysprocessen resulterade i fyra kategorier: Fysioterapeutens roll i patientmötet, Känslomässigt arbete, Framgångsfaktorer inom vården av förlossningsskador och Utmaningar inom vården av förlossningsskador med elva tillhörande subkategorier. Konklusion: Fysioterapeuterna har en betydande roll och kompetens som kan göra skillnad för patienter med förlossningsskador. De drivs av ett stort engagemang och vill se vidare utveckling av området samt stärka fysioterapeutens roll inom vården av förlossningsskador. Det behövs vidare forskning för att fylla kunskapsluckan av fysioterapeuters arbete med förlossningsskador. / Background: Pelvic floor dysfunction (PFD) after giving birth causes physical and mental discomfort. The injuries vary and the healthcare afterward is important for the mother´s rehabilitation. The competence of physiotherapists is suitable for the examination and treatment of PFD after giving birth. However, the profession is not established in this area. There are knowledge gaps about the physiotherapist's views and experiences of working with PFD after giving birth. Purpose: The purpose of this study was to describe the physiotherapist's views and experiences of working in Swedish healthcare with women with PFD after giving birth. Method: The study was a semi-structured qualitative interview study that included five participants who work with PFD after giving birth. The participants were recruited via the competence map for women's health on Fysioterapeuternas' website and via the Facebook group “Fysioterapeuter inom kvinnors hälsa”. Samples of convenience was applied. Data processing of the interview material was done through a qualitative content analysis. Results: The analysis process resulted in four categories: The physiotherapist's role when meeting patients, Emotional work, Successful factors in the healthcare of PFD after giving birth and Challenges in the healthcare of PFD after giving birth divided into eleven subcategories.  Conclusion: Physiotherapists have a significant role and the competence to make a difference for patients with PFD after giving birth. They are driven by commitment and want to see a further development of women’s health as well as strengthen the physiotherapist's role in maternity care. Further research is needed to fill the knowledge gap of physiotherapists' work with PFD after giving birth.

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

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The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.

A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.