Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.

Thesis (M. Eng.)--Carleton University, 1988. / Also available in electronic format on the Internet.

Thesis (M. Eng.)--Carleton University, 1989. / Also available in electronic format on the Internet.

Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 1990. / Chairman: Fred C. Lee. Includes bibliographical references.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 146-149). Also available in electronic version.

International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / A switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.

A novel, variable-gain switched-capacitor DC-DC converter is designed, constructed and tested. The proposed converter minimizes many of the problems which have traditionally hindered switched-capacitor DC-DC converters. The converter has high efficiency, strong regulation and low output voltage ripple across a wide variation in the line and load. The converter utilizes an optimized switching configuration that contains the maximum number of ideal conversion ratios for the given number of capacitors driven by a two-phase clock. The switched-capacitor converter is controlled by a gain-hopping feedforward control scheme in conjunction with duty-cycle, pulse-width modulation feedback control. The proposed control technique enhances the efficiency and regulation capability of switched-capacitor DC-DC converters, which are typically limited when there is a large variation in the line. Because the converter is optimized, programmable and capable of providing buck and/or boost operation (stepping-up and/or stepping-down the input voltage), the new switched-capacitor DC-DC converter is well-suited for a variety of applications and operating conditions. In addition, a novel algorithm based on graph theory and network analysis is developed which enumerates all possible ideal conversion ratios for a given switched-capacitor DC-DC converter structure. In particular, this algorithm can be used as a design tool to greatly improve the operation of multi-gain switched-capacitor converters, where the aim is to maximize the number of ideal conversion ratios while minimizing the number of switches and capacitors. Furthermore, the structure of all attainable positive, ideal conversion ratios of a two-phase switched-capacitor DC-DC converter, utilizing up to five capacitors, is enumerated. As a result, the design process for switched-capacitor converters is greatly simplified and a suitable converter structure can be more easily selected for a given application. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-03 23:27:24.183

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block of these circuits. This thesis studies gain stages that eliminate the internal compensation, thus allowing the SC circuits to operate at significantly higher operating speeds. An inverter-based SC integrator is presented. The proposed SC integrator is built with a pseudo-differential structure to improve its rejection of common-mode noise, such as charge injection and clock feedthrough. The proposed integrator also incorporates correlated double sampling (CDS) to boost its effective DC gain. Clock-boosting and switch bootstrapping techniques are not used in the proposed circuit, even though it uses a low supply voltage. To verify the speed advantage of the proposed circuit, a high speed delta sigma (Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation and layout floorplan are described. The design is based on MATLAB and SpectreS simulations. / Graduation date: 2002

Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent current, minimal external components and low cost. In this thesis, two step-down switched capacitor DC/DC converters are designed. One has the fixed output options 1.5V, 1.8V and 2.0V. The other one has the output 1.2V. These two converters are implemented in 0.5��m CMOS process through National Semiconductor Corporation. The design is verified by the circuit-level simulations, and design issues are discussed. / Graduation date: 2004