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In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Sandia National Laboratories (SNL) currently achieves a bandwidth efficiency (h ) of 0.5 to 1.0 bps/Hz by using traditional modulation schemes, such as, BPSK and QFSK. SNL has an interest in increasing the present bandwidth efficiency by a factor of 4 or higher with the same allocated bandwidth (about 10 MHz). Simulations have shown that 32- QAM trellis-coded modulation (TCM) gives a good bit error rate (BER) performance, and meets the requirements as far as the bandwidth efficiency is concerned. Critical to achieving this is that the receiver be able to achieve timing synchronization. This paper examines a particular timing recovery algorithm for all-digital receivers. Timing synchronization in a digital receiver can be achieved in different ways. One way of achieving this is by interpolating the original sampled sequence to produce another sampled sequence synchronized to the symbol rate or a multiple of the symbol rate. An adaptive sampling conversion algorithm which performs this function was developed by Floyd Gardner in 1993. In the present work, his algorithm was applied to two different modulation schemes, BPSK and 4-ary PAM. The two schemes were simulated in the presence of AWGN and ISI along with Gardner’s algorithm for timing recovery, and a fractionally spaced equalizer (T/2 FSE) for equalization. Simulations show that the algorithm gives good BER performance for BPSK in all the situations, and at different sampling frequencies, but unfortunately poor performance for the 4-ary PAM scheme. This indicates that Gardner’s algorithm for sampling conversion is not suitable for multi-level signaling schemes.

Η παρούσα διπλωματική εργασία αφορά στην πειραματική αξιολόγηση του μηχανισμού ανάκτησης ρυθμού συμβόλου για ψηφιακούς δέκτες τεχνολογίας SDR που λαμβάνουν δεδομένα μέσω δορυφόρου. Η ορολογία SDR/SR (Software Defined Radio/Software Radio) χρησιμοποιείται για να χαρακτηρίσει τους πομποδέκτες που μπορούν να καθορίζουν σημαντικές παραμέτρους τους και βασικές αρχές της λειτουργίας τους μέσω αναβάθμισης ή ενημέρωσης του λογισμικού τους. Ο μηχανισμός ανάκτησης του ρυθμού συμβόλου (Symbol Timing Recovery, STR) αναπτύχθηκε στα πλαίσια της διδακτορικής διατριβής του διδάκτορος Παναγιώτη Σαββόπουλου. Η παρούσα εργασία μελετά τη σύγκλιση του βρόχου υπό συνθήκες παραμένοντος σφάλματος συχνότητας καθώς επίσης και τον προσδιορισμό του λόγου σήματος προς θόρυβο στην έξοδο του βρόχου κάνοντας χρήση ενός νέου μεγέθους, metric, το οποίο έχει εισαχθεί στα πλαίσια της προαναφερθείσας διδακτορικής διατριβής, υπό συνθήκες λευκού Gaussian θορύβου. Το μέγεθος αυτό είναι σε θέση να δώσει αξιόπιστα αποτελέσματα στις ενδιάμεσες υπομονάδες του δέκτη υπό συνθήκες παραμένοντος σφάλματος συχνότητας. Στην παρούσα εργασία μελετώνται οι QPSK, 8PSK, 16-APSK και 32-APSK διαμορφώσεις διότι αυτές οι διαμορφώσεις χρησιμοποιούνται από το πρότυπο DVB-S2. / The purpose of this project is the experimental evaluation of a mechanism for the symbol timing recovery which is used in digital Software Defined Radio receivers. SDR/SR (Software Defined Radio/Software Radio) technology is used to characterise the transmitters and the receivers which are able to determine important parameters and basic primciples for their function through upgrade or briefing of their software. The symbol timing recovery mechanism (STR) was developped in terms of the doctora of dr Panagiotis Savopoylos. The precent project examines the loop’s convergence when there is frequency error as well as the signal to noise ratio in the output of STR with the use of a new size, metric, which was also developped in terms of the doctora which was mentioned before, when there is white Gaussian noise. The metric is able to give reliable results in the intermediate stages of the receiver when there is frequency error. In the precent project are examined the QPSK, 8PSK,16-APSK, 32-APSK modulations because these modulations are used in DVB-S2 standard.

In this thesis, symbol timing recovery based on matched filtering in Gaussian Minimum Shift Keying (GMSK) with bandwidth-bit period product (BT) of 0.3 is investigated. GMSK is the standard modulation type for GSM. Although GMSK modulation is non-linear, it is approximated to Offset Quadrature Amplitude Modulation (OQAM), which is a linear modulation, so that Maximum Likelihood Sequence Estimation (MLSE) method is possible in the receiver part. In this study Typical Urban (TU) channel model developed in COST 207 is used. Two methods are developed on the construction of the matched filter. In order to obtain timing recovery for GMSK signals, these methods are investigated. The fractional time delays are acquired by using interpolation and an iterative maximum search process. The performance of the proposed symbol timing recovery (STR) scheme is assessed by using computer simulations. It is observed that the STR tracks the variations of the frequency selective multipath fading channels almost the same as the Mazo criterion.

In this thesis, two key issues regarding M-ary orthogonal signaling systems, namely channel estimation and symbol timing recovery are investigated. Kasami codes, which are also called quasi orthogonal codes, are used for transmission of the information in place of orthogonal waveforms. In order to achieve symbol synchronization, a timing recovery scheme based on the Maximum Likelihood (ML) estimation of timing offset is proposed and the effects of proposed structure over the receiver performance are examined by using computer simulations. Moreover, the receiver performance of M-ary orthogonal signals transmitted over multipath fading channel is investigated. Least Square (LS) approach, based on the transmission of known training sequence, is used to estimate the channel impulse response. In addition to this, frame synchronization is employed at the receiver to extract the timing information by determining the start time of the received symbols. Computer simulations related to the proposed receiver structure are carried out in order to observe how the system performance is affected under multipath fading channel. Parameter selection guides regarding a good performance are also provided.