Distributed directory services are an evolving paradigm in the distributed computing arena. They are a shift from the centralized directory that causes delay and does not scale well to widespread peer-to-peer networks. With networking becoming more pervasive, there is a need to integrate the heterogeneity of device, data and network with the applications that are built on them. SyD or System on Mobile Devices is a middleware that is being used to implement such a distributed directory service. To provide a persistent global view of data, we serialize and synchronize the distributed directories. The SyD APIs provide a high-level environment to rapidly develop collaborative applications for such networks in a systematic manner. An intervehicle communication application that notifies the driver of a vehicle of the available parking spots in the vicinity, allows us to see the practical working and benefits of the distributed directory paradigm.

Wireless sensor networks (WSNs) consist of a large number of sensor nodes, capable of on-board sensing and data processing, that are employed to observe some phenomenon of interest. With their desirable properties of flexible deployment, resistance to harsh environment and lower implementation cost, WSNs envisage a plethora of applications in diverse areas such as industrial process control, battle- field surveillance, health monitoring, and target localization and tracking. Much of the sensing and communication paradigm in WSNs involves ensuring power efficient transmission and finding scalable algorithms that can deliver the desired performance objectives while minimizing overall energy utilization. Since power is primarily consumed in radio transmissions delivering timing information, clock synchronization represents an indispensable requirement to boost network lifetime. This dissertation focuses on deriving efficient estimators and performance bounds for the clock parameters in a classical frequentist inference approach as well as in a Bayesian estimation framework. A unified approach to the maximum likelihood (ML) estimation of clock offset is presented for different network delay distributions. This constitutes an analytical alternative to prior works which rely on a graphical maximization of the likelihood function. In order to capture the imperfections in node oscillators, which may render a time-varying nature to the clock offset, a novel Bayesian approach to the clock offset estimation is proposed by using factor graphs. Message passing using the max-product algorithm yields an exact expression for the Bayesian inference problem. This extends the current literature to cases where the clock offset is not deterministic, but is in fact a random process. A natural extension of pairwise synchronization is to develop algorithms for the more challenging case of network-wide synchronization. Assuming exponentially distributed random delays, a network-wide clock synchronization algorithm is proposed using a factor graph representation of the network. Message passing using the max- product algorithm is adopted to derive the update rules for the proposed iterative procedure. A closed form solution is obtained for each node's belief about its clock offset at each iteration. Identifying the close connections between the problems of node localization and clock synchronization, we also address in this dissertation the problem of joint estimation of an unknown node's location and clock parameters by incorporating the effect of imperfections in node oscillators. In order to alleviate the computational complexity associated with the optimal maximum a-posteriori estimator, two iterative approaches are proposed as simpler alternatives. The first approach utilizes an Expectation-Maximization (EM) based algorithm which iteratively estimates the clock parameters and the location of the unknown node. The EM algorithm is further simplified by a non-linear processing of the data to obtain a closed form solution of the location estimation problem using the least squares (LS) approach. The performance of the estimation algorithms is benchmarked by deriving the Hybrid Cramer-Rao lower bound (HCRB) on the mean square error (MSE) of the estimators. We also derive theoretical lower bounds on the MSE of an estimator in a classical frequentist inference approach as well as in a Bayesian estimation framework when the likelihood function is an arbitrary member of the exponential family. The lower bounds not only serve to compare various estimators in our work, but can also be useful in their own right in parameter estimation theory.

The pharmacological development of non-steroidal contraceptives has yet to be achieved. Arresting oocyte maturation without blocking ovulation has been evaluated using different inhibitors of the phosphodiesterase 3A (PDE3A). Unfortunately, PDE3A is also expressed in the heart and blood vessels, and inhibition of PDE3A in oocytes can produce cardiovascular side effects. We reviewed the literature on available PDE3 inhibitors and selected cilostazol (CLZ), which is an FDA approved therapeutic. CLZ has the ability to decrease cellular adenosine uptake and consequently antagonizes side effects of PDE3A inhibition in vital organs. CLZ inhibited oocyte meiotic maturation in vitro. CLZ has more degenerative impact on arrested oocytes than matured oocytes, indicating that prolonged meiotic arrest of oocytes is harmful. Administration of CLZ any time from 9h before the ovulatory stimulus to 4h after the stimulus resulted in ovulation of immature oocytes. Controlling CLZ dose, time of CLZ administration, and time of oocyte collection resulted in ovulation of oocytes at different meiotic stages. Oral administrations of CLZ in naturally cycling mice were also observed to block pregnancy whereas remating of those previously treated females resulted in normal offspring and litter sizes. Therefore, CLZ does not only have a wide margin of contraception but also is reversible. Ovulated immature oocytes were observed to have higher rates of advanced chromatin configuration and cortical granule distribution, normal spindle and chromosomal organization, maturation, and in vitro fertilization (IVF) than ovarian immature oocytes. Ovulated metaphase I oocytes that were matured in vitro or in vivo had higher IVF rates than ovulated mature oocytes. Ovulated germinal vesicle (GV) oocytes that were in vitro matured also showed higher IVF rates but when in vivo matured, they had lower IVF rates than ovulated mature oocytes because of the high degeneration and low fertilization rates associated with in vivo maturation of GV oocytes. In summary, CLZ merits further evaluation as a non-steroidal contraceptive and is capable of producing oocytes of various meiotic stages with advanced developmental features.

Wireless communication systems such as multipoint communication systems (MCS) are becoming attractive as cost-effective means for providing network access in sparsely populated, rugged, or developing areas of the world. Since the radio spectrum is limited, it is desirable to use spectrally efficient modulation methods such as quadrature amplitude modulation (QAM) for high data rate channels. Many MCS employ time division multiple access (TDMA) and/or time division duplexing (TDD) techniques, in which transmissions operate in bursts. In many cases, a preamble of known symbols is appended to the beginning of each burst for carrier and symbol timing recovery (symbol timing is assumed known in this thesis). Preamble symbols consume bandwidth and power and are not used to convey information. In order for burst-mode communications to provide efficient data throughput, the synchronization time must be short compared to the user data portion of the burst. <p> Traditional methods of communication system synchronization such as phase-locked loops (PLLs) have demonstrated reduced performance when operated in burst-mode systems. In this thesis, a feedforward (FF) digital carrier recovery technique to achieve rapid carrier synchronization is proposed. The estimation algorithms for determining carrier offsets in carrier acquisition and tracking in a linear channel environment corrupted by additive white Gaussian noise (AWGN) are described. The estimation algorithms are derived based on the theory of maximum likelihood (ML) parameter estimation. The estimations include data-aided (DA) carrier frequency and phase estimations in acquisition and non-data-aided (NDA) carrier phase estimation in tracking. The DA carrier frequency and phase estimation algorithms are based on oversampling of a known preamble. The NDA carrier phase estimation makes use of symbol timing knowledge and estimates are extracted from the random data portion of the burst. The algorithms have been simulated and tested using Matlab® to verify their functionalities. The performance of these estimators is also evaluated in the burst-mode operations for 16-QAM and compared in the presence of non-ideal conditions (frequency offset, phase offset, and AWGN). The simulation results show that the carrier recovery techniques presented in this thesis proved to be applicable to the modulation schemes of 16-QAM. The simulations demonstrate that the techniques provide a fast carrier acquisition using a short preamble (about 111 symbols) and are suitable for burst-mode communication systems.

Transactional memory (TM) systems have gained considerable popularity in the last decade driven by the increased demand for tools that ease parallel programming. TM eliminates the need for user-locks that protect accesses to shared data. It offers performance close to that of fine-grain locking with the programming simplicity of coarse-grain locking. Today’s TM systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict occurs. 2PL is a simple algorithm that provides fast transactional operations. However, it limits concurrency in applications with high contention because it increases the rate of aborts. We propose the use of a more relaxed concurrency control algorithm to provide better concurrency. This algorithm is based on the conflict-serializability (CS) model. Unlike 2PL, it allows some transactions to commit successfully even when they make conflicting accesses. We implement this algorithm both in a software TM system as well as in a simulator of a hardware TM system. Our evaluation using TM benchmarks shows that the algorithm improves the performance of applications with long transactions and high abort rates. Performance is improved by up to 299% in the software TM, and up to 66% in the hardware simulator. We argue that these improvements come with little additional complexity and require no changes to the transactional programming model. This makes our implementation feasible

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

In this thesis, we study parallelization of multiplayer games using software Transactional Memory (STM) support. We show that STM provides not only ease of programming, but also better scalability than achievable with state-of-the-art lock-based programming for this realistic high impact application. We evaluate and compare two parallel implementations of a simplified version (named SynQuake) of the popular game Quake. While in STM SynQuake support for maintaining consistency of each potentially complex game action is automatic, conservative locking of surrounding objects within a bounding-box for the duration of the game action is inherently needed in lock-based SynQuake. This leads to higher scalability of STM SynQuake versus lock-based SynQuake due to increased false sharing in the latter. Task assignment to threads has a second-order effect on scalability of STM-SynQuake, impacting the application's true sharing patterns. We show that a locality-aware task assignment provides the best trade-off between load balancing and conflict reduction.

Transactional memory (TM) systems have gained considerable popularity in the last decade driven by the increased demand for tools that ease parallel programming. TM eliminates the need for user-locks that protect accesses to shared data. It offers performance close to that of fine-grain locking with the programming simplicity of coarse-grain locking. Today’s TM systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict occurs. 2PL is a simple algorithm that provides fast transactional operations. However, it limits concurrency in applications with high contention because it increases the rate of aborts. We propose the use of a more relaxed concurrency control algorithm to provide better concurrency. This algorithm is based on the conflict-serializability (CS) model. Unlike 2PL, it allows some transactions to commit successfully even when they make conflicting accesses. We implement this algorithm both in a software TM system as well as in a simulator of a hardware TM system. Our evaluation using TM benchmarks shows that the algorithm improves the performance of applications with long transactions and high abort rates. Performance is improved by up to 299% in the software TM, and up to 66% in the hardware simulator. We argue that these improvements come with little additional complexity and require no changes to the transactional programming model. This makes our implementation feasible

Context represents any knowledge obtained from Wireless Sensor Networks (WSNs) about the object being monitored (such as time and location of the sensed events). Time and location are important constituents of context as the information about the events sensed in WSNs is comprehensive when it includes spatio-temporal knowledge. In this thesis, we first concentrate on the development of a suite of lightweight algorithms on temporal event ordering and time synchronization as well as localization for WSNs. Then, we propose an energy-efficient clustering routing protocol for WSNs that is used for message delivery in the former algorithm. The two problems - temporal event ordering and synchronization - are dealt with together as both are concerned with preserving temporal relationships of events in WSNs. The messages needed for synchronization are piggybacked onto the messages exchanged in underlying algorithms. The synchronization algorithm is tailored to the clustered topology in order to reduce the overhead of keeping WSNs synchronized. The proposed localization algorithm has an objective of lowering the overhead of DV-hop based algorithms by reducing the number of floods in the initial position estimation phase. It also randomizes iterative refinement phase to overcome the synchronicity of DV-hop based algorithms. The position estimates with higher confidences are emphasized to reduce the impact of erroneous estimates on the neighbouring nodes. The proposed clustering routing protocol is used for message delivery in the proposed temporal algorithm. Nearest neighbour nodes are employed for inter-cluster communication. The algorithm provides Quality of Service by forwarding high priority messages via the paths with the least cost. The algorithm is also extended for multiple Sink scenario. The suite of algorithms proposed in this thesis provides the necessary tool for providing spatio-temporal context for context-aware WSNs. The algorithms are lightweight as they aim at satisfying WSN's requirements primarily in terms of energy-efficiency, low latency and fault tolerance. This makes them suitable for emergency response applications and ubiquitous computing.