With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is significantly increasing in order to achieve a good yield. Consequently design companies need to further lower power consumption. All these factors bring new challenges; simulation and modeling need to handle more design constraints, and need to work with modern manufacturing processes. In this dissertation, algorithms and new methodology are presented for these problems: (1) fast and accurate capacitance extraction, (2) capacitance extraction considering lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access memory) performance and yield, and (4) new physical synthesis optimization flow is used to shed area and reduce the power consumption. Interconnect parasitic extraction plays an important role in simulation, verification, optimization. A fast and accurate parasitic extraction algorithm is always important for a current design automation tool. In this dissertation, we propose a new algorithm named HybCap to efficiently handle multiple planar, conformal or embedded dielectric media. From experimental results, the new method is significantly faster than the previous one, 77X speedup, and has a 99% memory savings compared with FastCap and 2X speedup, and has an 80% memory savings compared with PHiCap for complex dielectric media. In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction) flow, a modified LPE flow and fast algorithms for interconnect parasitic extraction are proposed in this dissertation. Our methodology is efficient, compatible with the existing design flow and has high accuracy. With the new enhanced parasitic extraction flow, simulation of BEOL effect on SRAM performance becomes possible. A SRAM simulation model with internal cell interconnect RC parasitics is proposed in order to study the BEOL lithography impact. The impact of BEOL variations on memory designs are systematically evaluated in this dissertation. The results show the power estimation with our SRAM model is more accurate. Finally, a new optimization flow to shed area blow in the design synthesis flow is proposed, which is one level beyond simulation and modeling to directly optimize design, but is also built upon accurate simulations and modeling. Two simple, yet efficient, buffering and gate sizing techniques are presented. On 20 industrial designs in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8% total area reduction, 10% wirelength reduction and 770 ps worst slack improvement on average.

Este trabalho apresenta o desenvolvimento de um fluxo de projeto de circuitos digitais integrados, visando a incluir células geradas automaticamente pela ferramenta ASTRAN. Como parte integrante deste novo fluxo, desenvolveu-se uma nova técnica de comparação entre células, utilizando Redes Neurais Artificiais, para a modelagem das células ASTRAN, esta técnica se mostrou flexível ao se adaptar a diversos tipos de células e com resultados robustos tendo 5% de desvio padrão e 4% para o erro relativo. Também, foi criada uma ferramenta capaz de substituir células comerciais por células ASTRAN, tendo como objetivo melhorar as características de potência consumida e área utilizada pelo circuito, e por fim gerando um circuito misto composto de células comerciais feitas à mão e células ASTRAN geradas automaticamente. O foco principal deste trabalho encontra-se na integração do fluxo de geração de células geradas automaticamente a um fluxo de síntese comercial de circuitos digitais. Os resultados obtidos mostraram-se promissores, obtendo-se ganhos em redução de área e potência dos circuitos analisados. Em média os circuitos tiveram uma redução de 3,77% na potência consumida e 1,25% menos área utilizada. Com um acréscimo de 0,64% por parte do atraso total do circuito. / This work presents the development of a design flow for digital integrated circuits, including cells generated automatically by the ASTRAN tool. Moreover, a new technique, using Artificial Neural Networks, was developed to perform a comparison between two different cells, i.e. commercial and ASTRAN’s cell. This technique proved to be flexible when adapting to several types of cells and with robust results having 5% of standard deviation and 4% for relative error. Also, a new tool was developed, capable of performing cell replacement between ASTRAN and commercial cells, to improve power consumption an used area. Finally a mixed circuit composed of handmade commercial cells and cells automatically generated by ASTRAN was generated. A target was to mix an automatic cell synthesis tool with commercial synthesis tools dedicated to standard cells. Comparisons have shown that our approach was able to produce satisfactory results related area and power consumption. In average the circuits had a reduction of 3.77% in the power consumed and 1.25% less used area. With an increase of 0.64% due to the total delay of the circuit.

Este trabalho apresenta o desenvolvimento de um fluxo de projeto de circuitos digitais integrados, visando a incluir células geradas automaticamente pela ferramenta ASTRAN. Como parte integrante deste novo fluxo, desenvolveu-se uma nova técnica de comparação entre células, utilizando Redes Neurais Artificiais, para a modelagem das células ASTRAN, esta técnica se mostrou flexível ao se adaptar a diversos tipos de células e com resultados robustos tendo 5% de desvio padrão e 4% para o erro relativo. Também, foi criada uma ferramenta capaz de substituir células comerciais por células ASTRAN, tendo como objetivo melhorar as características de potência consumida e área utilizada pelo circuito, e por fim gerando um circuito misto composto de células comerciais feitas à mão e células ASTRAN geradas automaticamente. O foco principal deste trabalho encontra-se na integração do fluxo de geração de células geradas automaticamente a um fluxo de síntese comercial de circuitos digitais. Os resultados obtidos mostraram-se promissores, obtendo-se ganhos em redução de área e potência dos circuitos analisados. Em média os circuitos tiveram uma redução de 3,77% na potência consumida e 1,25% menos área utilizada. Com um acréscimo de 0,64% por parte do atraso total do circuito. / This work presents the development of a design flow for digital integrated circuits, including cells generated automatically by the ASTRAN tool. Moreover, a new technique, using Artificial Neural Networks, was developed to perform a comparison between two different cells, i.e. commercial and ASTRAN’s cell. This technique proved to be flexible when adapting to several types of cells and with robust results having 5% of standard deviation and 4% for relative error. Also, a new tool was developed, capable of performing cell replacement between ASTRAN and commercial cells, to improve power consumption an used area. Finally a mixed circuit composed of handmade commercial cells and cells automatically generated by ASTRAN was generated. A target was to mix an automatic cell synthesis tool with commercial synthesis tools dedicated to standard cells. Comparisons have shown that our approach was able to produce satisfactory results related area and power consumption. In average the circuits had a reduction of 3.77% in the power consumed and 1.25% less used area. With an increase of 0.64% due to the total delay of the circuit.

Este trabalho apresenta o desenvolvimento de um fluxo de projeto de circuitos digitais integrados, visando a incluir células geradas automaticamente pela ferramenta ASTRAN. Como parte integrante deste novo fluxo, desenvolveu-se uma nova técnica de comparação entre células, utilizando Redes Neurais Artificiais, para a modelagem das células ASTRAN, esta técnica se mostrou flexível ao se adaptar a diversos tipos de células e com resultados robustos tendo 5% de desvio padrão e 4% para o erro relativo. Também, foi criada uma ferramenta capaz de substituir células comerciais por células ASTRAN, tendo como objetivo melhorar as características de potência consumida e área utilizada pelo circuito, e por fim gerando um circuito misto composto de células comerciais feitas à mão e células ASTRAN geradas automaticamente. O foco principal deste trabalho encontra-se na integração do fluxo de geração de células geradas automaticamente a um fluxo de síntese comercial de circuitos digitais. Os resultados obtidos mostraram-se promissores, obtendo-se ganhos em redução de área e potência dos circuitos analisados. Em média os circuitos tiveram uma redução de 3,77% na potência consumida e 1,25% menos área utilizada. Com um acréscimo de 0,64% por parte do atraso total do circuito. / This work presents the development of a design flow for digital integrated circuits, including cells generated automatically by the ASTRAN tool. Moreover, a new technique, using Artificial Neural Networks, was developed to perform a comparison between two different cells, i.e. commercial and ASTRAN’s cell. This technique proved to be flexible when adapting to several types of cells and with robust results having 5% of standard deviation and 4% for relative error. Also, a new tool was developed, capable of performing cell replacement between ASTRAN and commercial cells, to improve power consumption an used area. Finally a mixed circuit composed of handmade commercial cells and cells automatically generated by ASTRAN was generated. A target was to mix an automatic cell synthesis tool with commercial synthesis tools dedicated to standard cells. Comparisons have shown that our approach was able to produce satisfactory results related area and power consumption. In average the circuits had a reduction of 3.77% in the power consumed and 1.25% less used area. With an increase of 0.64% due to the total delay of the circuit.

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