As a CAD tool, the Computer Aided Model Structuring System (call MOSTS in the following text) for model structuring in system design and system simulation has been designed and implemented. First, this MOSTS allows system design experts to create and save System Data Bases (SDBs) for model structuring in system design and simulation. Then, these SDBs can be retrieved, modified, and finally used to structure system models by design engineers. The MOSTS pursues the model structuring process in such a way that the model structure having the best performance (according to the expert's knowledge and the design engineer's design criteria) will be generated first, and then the second best model, the third best model, and so on.

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In this dissertation, we consider analytic and numeric approaches to the solution of probabilistic steady-state problems with specific applications in simulation and queueing theory. Our first objective on steady-state simulations is to develop new estimators for the variance parameter of a selected output process that have better performance than certain existing variance estimators in the literature. To complete our analysis of these new variance estimators, called linear combinations of overlapping variance estimators, we do the following: establish theoretical asymptotic properties of the new estimators; test the theoretical results on a battery of examples to see how the new estimators perform in practice; and use the estimators for confidence interval estimation for both the mean and the variance parameter. Our theoretical and empirical results indicate the new estimators' potential for improvements in accuracy and computational efficiency. Our second objective on steady-state simulations is to derive the expected values of various competing estimators for the variance parameter. In this research, we do the following: formulate the machinery to calculate the exact expected value of a given estimator for the variance parameter; calculate the exact expected values of various variance estimators in the literature; compute these expected values for certain stochastic processes with complicated covariance functions; and derive expressions for the mean squared error of the estimators studied herein. We find that certain standardized time series estimators outperform their competitors as the sample size becomes large. Our research on queueing theory focuses on pricing of the service provided to individual customers in a queueing system. We find sensitivity results that enable efficient computational procedures for dynamic pricing decisions for maximizing the long-run average reward in a queueing facility with the following properties: there are a fixed number of servers, each with the same constant service rate; the system has a fixed finite capacity; the price charged to a customer entering the system depends on the number of customers in the system; and the customer arrival rate depends on the current price of the service. We show that the sensitivity results considered significantly reduce the computational requirements for finding the optimal pricing policies.

Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best ways to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This research explores new computer-aided design algorithms for developing optoelectronic systems. These algorithms focus on place and route problems using optical interconnections covering system-on-a-chip design as well as system-on-a-package design. In order to design optoelectronic systems, optical interconnection models are developed at first. The CAD algorithms include optical interconnection models and solve place and route problems for optoelectronic systems. The MCNC and GSRC benchmark circuits are used to evaluate these algorithms.