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Performance modelling and high performance buffer design for the system with network on chipLiu, Jin, January 2007 (has links) (PDF)
Thesis (Ph. D.)--Washington State University, December 2007. / Includes bibliographical references (p. 107-112).
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Dynamics and control of microchemical systems : From reduced-order theoretical approaches to embedded model predictive control /Bleris, Leonidas G. January 2006 (has links)
Thesis (Ph. D.)--Lehigh University, 2006. / Includes vita. Includes bibliographical references (leaves 173-191).
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Automating layout of reconfigurable subsystems for systems-on-a-chip /Phillips, Shawn A. January 2004 (has links)
Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 141-147).
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Transient error resilience in network-on-chip communication fabricsGanguly, Amlan, January 2007 (has links) (PDF)
Thesis (M.S. in electrical engineering)--Washington State University, May 2007. / Includes bibliographical references (p. 70-73).
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Lifetime reliability of multi-core systems: modeling and applications.January 2011 (has links)
Huang, Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 218-232). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Preface --- p.1 / Chapter 1.2 --- Background --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.3.1 --- Lifetime Reliability Modeling --- p.6 / Chapter 1.3.2 --- Simulation Framework --- p.7 / Chapter 1.3.3 --- Applications --- p.9 / Chapter 1.4 --- Thesis Outline --- p.10 / Chapter I --- Modeling --- p.12 / Chapter 2 --- Lifetime Reliability Modeling --- p.13 / Chapter 2.1 --- Notation --- p.13 / Chapter 2.2 --- Assumption --- p.16 / Chapter 2.3 --- Introduction --- p.16 / Chapter 2.4 --- Related Work --- p.19 / Chapter 2.5 --- System Model --- p.21 / Chapter 2.5.1 --- Reliability of A Surviving Component --- p.22 / Chapter 2.5.2 --- Reliability of a Hybrid k-out-of-n:G System --- p.26 / Chapter 2.6 --- Special Cases --- p.31 / Chapter 2.6.1 --- Case I: Gracefully Degrading System --- p.31 / Chapter 2.6.2 --- Case II: Standby Redundant System --- p.33 / Chapter 2.6.3 --- Case III: l-out-of-3:G System with --- p.34 / Chapter 2.7 --- Numerical Results --- p.37 / Chapter 2.7.1 --- Experimental Setup --- p.37 / Chapter 2.7.2 --- Experimental Results and Discussion --- p.40 / Chapter 2.8 --- Conclusion --- p.43 / Chapter 2.9 --- Appendix --- p.44 / Chapter II --- Simulation Framework --- p.47 / Chapter 3 --- AgeSim: A Simulation Framework --- p.48 / Chapter 3.1 --- Introduction --- p.48 / Chapter 3.2 --- Preliminaries and Motivation --- p.51 / Chapter 3.2.1 --- Prior Work on Lifetime Reliability Analysis of Processor- Based Systems --- p.51 / Chapter 3.2.2 --- Motivation of This Work --- p.53 / Chapter 3.3 --- The Proposed Framework --- p.54 / Chapter 3.4 --- Aging Rate Calculation --- p.57 / Chapter 3.4.1 --- Lifetime Reliability Calculation --- p.58 / Chapter 3.4.2 --- Aging Rate Extraction --- p.60 / Chapter 3.4.3 --- Discussion on Representative Workload --- p.63 / Chapter 3.4.4 --- Numerical Validation --- p.65 / Chapter 3.4.5 --- Miscellaneous --- p.66 / Chapter 3.5 --- Lifetime Reliability Model for MPSoCs with Redundancy --- p.68 / Chapter 3.6 --- Case Studies --- p.70 / Chapter 3.6.1 --- Dynamic Voltage and Frequency Scaling --- p.71 / Chapter 3.6.2 --- Burst Task Arrival --- p.75 / Chapter 3.6.3 --- Task Allocation on Multi-Core Processors --- p.77 / Chapter 3.6.4 --- Timeout Policy on Multi-Core Processors with Gracefully Degrading Redundancy --- p.78 / Chapter 3.7 --- Conclusion --- p.79 / Chapter 4 --- Evaluating Redundancy Schemes --- p.83 / Chapter 4.1 --- Introduction --- p.83 / Chapter 4.2 --- Preliminaries and Motivation --- p.85 / Chapter 4.2.1 --- Failure Mechanisms --- p.85 / Chapter 4.2.2 --- Related Work and Motivation --- p.86 / Chapter 4.3 --- Proposed Analytical Model for the Lifetime Reliability of Proces- sor Cores --- p.88 / Chapter 4.3.1 --- "Impact of Temperature, Voltage, and Frequency" --- p.88 / Chapter 4.3.2 --- Impact of Workloads --- p.92 / Chapter 4.4 --- Lifetime Reliability Analysis for Multi-core Processors with Vari- ous Redundancy Schemes --- p.95 / Chapter 4.4.1 --- Gracefully Degrading System (GDS) --- p.95 / Chapter 4.4.2 --- Processor Rotation System (PRS) --- p.97 / Chapter 4.4.3 --- Standby Redundant System (SRS) --- p.98 / Chapter 4.4.4 --- Extension to Heterogeneous System --- p.99 / Chapter 4.5 --- Experimental Methodology --- p.101 / Chapter 4.5.1 --- Workload Description --- p.102 / Chapter 4.5.2 --- Temperature Distribution Extraction --- p.102 / Chapter 4.5.3 --- Reliability Factors --- p.103 / Chapter 4.6 --- Results and Discussions --- p.103 / Chapter 4.6.1 --- Wear-out Rate Computation --- p.103 / Chapter 4.6.2 --- Comparison on Lifetime Reliability --- p.105 / Chapter 4.6.3 --- Comparison on Performance --- p.110 / Chapter 4.6.4 --- Comparison on Expected Computation Amount --- p.112 / Chapter 4.7 --- Conclusion --- p.118 / Chapter III --- Applications --- p.119 / Chapter 5 --- Task Allocation and Scheduling for MPSoCs --- p.120 / Chapter 5.1 --- Introduction --- p.120 / Chapter 5.2 --- Prior Work and Motivation --- p.122 / Chapter 5.2.1 --- IC Lifetime Reliability --- p.122 / Chapter 5.2.2 --- Task Allocation and Scheduling for MPSoC Designs --- p.124 / Chapter 5.3 --- Proposed Task Allocation and Scheduling Strategy --- p.126 / Chapter 5.3.1 --- Problem Definition --- p.126 / Chapter 5.3.2 --- Solution Representation --- p.128 / Chapter 5.3.3 --- Cost Function --- p.129 / Chapter 5.3.4 --- Simulated Annealing Process --- p.130 / Chapter 5.4 --- Lifetime Reliability Computation for MPSoC Embedded Systems --- p.133 / Chapter 5.5 --- Efficient MPSoC Lifetime Approximation --- p.138 / Chapter 5.5.1 --- Speedup Technique I - Multiple Periods --- p.139 / Chapter 5.5.2 --- Speedup Technique II - Steady Temperature --- p.139 / Chapter 5.5.3 --- Speedup Technique III - Temperature Pre- calculation --- p.140 / Chapter 5.5.4 --- Speedup Technique IV - Time Slot Quantity Control --- p.144 / Chapter 5.6 --- Experimental Results --- p.144 / Chapter 5.6.1 --- Experimental Setup --- p.144 / Chapter 5.6.2 --- Results and Discussion --- p.146 / Chapter 5.7 --- Conclusion and Future Work --- p.152 / Chapter 6 --- Energy-Efficient Task Allocation and Scheduling --- p.154 / Chapter 6.1 --- Introduction --- p.154 / Chapter 6.2 --- Preliminaries and Problem Formulation --- p.157 / Chapter 6.2.1 --- Related Work --- p.157 / Chapter 6.2.2 --- Problem Formulation --- p.159 / Chapter 6.3 --- Analytical Models --- p.160 / Chapter 6.3.1 --- Performance and Energy Models for DVS-Enabled Pro- cessors --- p.160 / Chapter 6.3.2 --- Lifetime Reliability Model --- p.163 / Chapter 6.4 --- Proposed Algorithm for Single-Mode Embedded Systems --- p.165 / Chapter 6.4.1 --- Task Allocation and Scheduling --- p.165 / Chapter 6.4.2 --- Voltage Assignment for DVS-Enabled Processors --- p.168 / Chapter 6.5 --- Proposed Algorithm for Multi-Mode Embedded Systems --- p.169 / Chapter 6.5.1 --- Feasible Solution Set --- p.169 / Chapter 6.5.2 --- Searching Procedure for a Single Mode --- p.171 / Chapter 6.5.3 --- Feasible Solution Set Identification --- p.171 / Chapter 6.5.4 --- Multi-Mode Combination --- p.177 / Chapter 6.6 --- Experimental Results --- p.178 / Chapter 6.6.1 --- Experimental Setup --- p.178 / Chapter 6.6.2 --- Case Study --- p.180 / Chapter 6.6.3 --- Sensitivity Analysis --- p.181 / Chapter 6.6.4 --- Extensive Results --- p.183 / Chapter 6.7 --- Conclusion --- p.185 / Chapter 7 --- Customer-Aware Task Allocation and Scheduling --- p.186 / Chapter 7.1 --- Introduction --- p.186 / Chapter 7.2 --- Prior Work and Problem Formulation --- p.188 / Chapter 7.2.1 --- Related Work and Motivation --- p.188 / Chapter 7.2.2 --- Problem Formulation --- p.191 / Chapter 7.3 --- Proposed Design-Stage Task Allocation and Scheduling --- p.192 / Chapter 7.3.1 --- Solution Representation and Moves --- p.193 / Chapter 7.3.2 --- Cost Function --- p.196 / Chapter 7.3.3 --- Impact of DVFS --- p.198 / Chapter 7.4 --- Proposed Algorithm for Online Adjustment --- p.200 / Chapter 7.4.1 --- Reliability Requirement for Online Adjustment --- p.201 / Chapter 7.4.2 --- Analytical Model --- p.203 / Chapter 7.4.3 --- Overall Flow --- p.204 / Chapter 7.5 --- Experimental Results --- p.205 / Chapter 7.5.1 --- Experimental Setup --- p.205 / Chapter 7.5.2 --- Results and Discussion --- p.207 / Chapter 7.6 --- Conclusion --- p.211 / Chapter 7.7 --- Appendix --- p.211 / Chapter 8 --- Conclusion and Future Work --- p.214 / Chapter 8.1 --- Conclusion --- p.214 / Chapter 8.2 --- Future Work --- p.215 / Bibliography --- p.232
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Systems-on-a-chip testing using an embedded microprocessorHwang, Sungbae. January 2002 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
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Test vector compression techniques for systems-on-chip /Jas, Abhijit, January 2001 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references (leaves 94-102). Available also in a digital version from Dissertation Abstracts.
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Dynamic memory management for embedded real-time multiprocessor system-on-a-chipShalan, Mohamed A. January 2003 (has links) (PDF)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Vincent Mooney, Committee Chair; John Barry, Committee Member; James Hamblen, Committee Member; Karsten Schwan, Committee Member; Linda Wills, Committee Member. Includes bibliography.
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A unified hardware-software framework for evaluating power consumption of embedded system-on-a-chip designsTalarico, Claudio January 2004 (has links)
Thesis (Ph. D.)--University of Hawaii at Manoa, 2004. / Includes bibliographical references (leaves 118-126). / Also available by subscription via World Wide Web / x, 126 leaves, bound ill. 29 cm
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A unified hardware-software framework for evaluating power consumption of embedded system-on-a-chip designsTalarico, Claudio. January 2004 (has links)
Thesis (Ph. D.)--University of Hawaii at Manoa, 2004. / Includes bibliographical references (leaves 118-126).
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