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Implementing matrix algorithms on matrix coprocessors /Clarke, Michael. Unknown Date (has links)
Thesis (MAppSc (Comp & InfoSc))--University of South Australia, 1997
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A self-timed implementation of the bi-way sorter systolic array processor /Diamond, Mitchell S. January 1993 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references.
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VLSI implementation of adaptive BIT/serial IIR filtersBadyal, Rajeev 29 January 1992 (has links)
A new structure for the implementation of bit/serial adaptive IIR filter is
presented. The bit level system consists of gated full adders for the arithmetic
unit and data latches for the data path. This approach allows recursive
operation of the IIR filter to be implemented without any global
interconnections, minimal delay time, chip area and I/O pins. The
coefficients of the filter can be updated serially in real time for time invariant
and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a
2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992
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Equivalence relations of synchronous schemes /Cirovic, Branislav, January 2000 (has links)
Thesis (Ph.D.), Memorial University of Newfoundland, 2000. / Includes index. Restricted until June 2001. Bibliography: leaves 82-84.
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Fully efficient pipelined VLSI arrays for solving toeplitz matricesLee, Louis Wai-Fung 11 October 1991 (has links)
Fully efficient systolic arrays for the solution of Toeplitz
matrices using Schur algorithm [1] have been obtained. By applying
clustering mapping method [2], the complexity of the algorithm is
0(n) and it requires n/2 processing elements as opposed to n
processing elements developed elsewhere [1].
The motivation of this thesis is to obtain efficient pipeline
arrays by using the synthesis procedure to implement Toeplitz
matrix solution. Furthermore, we will examine pipeline structures
for the Toeplitz system factorization and back-substitution by
obtaining clustering and Multi-Rate Array structures. These methods
reduce the number of processing elements and enhance the
computational speed. Comparison and advantage of these methods to
other method will be presented. / Graduation date: 1992
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