abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions. Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime. This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created. Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Le développement des technologies de communication et de l’information nécessite des composants semi-conducteurs ultrarapides et à faible niveau de bruit. Les transistors bipolaires à hétérojonction (TBH) sont des dispositifs qui visent des applications à hautes fréquences et qui peuvent satisfaire ces conditions. L’objet de cette thèse est l’étude expérimentale et la modélisation du bruit haute fréquence des TBH Si/SiGe:C (technologie STMicroelectronics) et InP/InGaAs (III-V Lab Alcatel-Thales).Accompagné d’un état de l’art des performances dynamiques des différentes technologies de TBH, le chapitre I rappelle brièvement le fonctionnement et la caractérisation des TBH en régime statique et dynamique. La première partie du chapitre II donne la description des deux types de TBH, avec l’analyse des performances dynamiques et statiques en fonction des variations technologiques de ceux-ci (composition de la base du TBH SiGe:C, réduction des dimensions latérales du TBH InGaAs). Avec l’aide d’une modélisation hydrodynamique, la seconde partie montre l’avantage d’une composition en germanium de 15-25% dans la base du TBH SiGe pour atteindre les meilleurs performances dynamiques. Le chapitre III synthétise des analyses statiques et dynamiques réalisées à basse température permettant de déterminer le poids relatif des temps de transit et des temps de charge dans la limitation des performances des TBH. L’analyse expérimentale et la modélisation analytique du bruit haute fréquence des deux types de TBH sont présentées en chapitre IV. La modélisation permet de mettre en évidence l’influence de la défocalisation du courant, de l’auto-échauffement, de la nature de l’hétérojonction base-émetteur sur le bruit haute fréquence. Une estimation des performances en bruit à basse température des deux types de TBH est obtenues avec les modèles électriques. / In order to fulfil the roadmap for the development of telecommunication and information technologies (TIC), low noise level and very fast semiconductor devices are required. Heterojunction bipolar transistor has demonstrated excellent high frequency performances and becomes a candidate to address TIC roadmap. This work deals with experimental analysis and high frequency noise modelling of Si/SiGe:C HBT (STMicroelectronics tech.) and InP/InGaAs HBT (III-V Lab Alcatel-Thales).Chapter I introduces the basic concepts of HBTs operation and the characterization at high-frequency. This chapter summarizes the high frequency performances of many state-of-the-art HBT technologies. The first part of chapter II describes the two HBT sets, with paying attention on the impact of the base composition (SiGe:C) or the lateral reduction of the device (InGaAs) on static and dynamic performances. Based on TCAD modelling, the second part shows that a 15-25% germanium composition profile in the base is able to reach highest dynamic performances. Chapter III summarizes the static and dynamic results at low temperature, giving a separation of the intrinsic transit times and charging times involved into the performance limitation. Chapter IV presents noise measurements and the derivation of high frequency noise analytical models. These models highlight the impact of the current crowding and the self-heating effects, and the influence of the base-emitter heterojunction on the high frequency noise. According to these models the high frequency noise performances are estimated at low temperature for both HBT technologies.