Threshold logic gates have the capability of realizing complex Boolean functions with smaller number of logic gates [1]. These gates are very sensitive to their weight values which may change during manufacturing process. So Threshold logic gates should be carefully designed to allow for maximum deviation from desired design weight values without affecting its functionality . This maximum allowable deviation is known as Fault Tolerance of the gate. ILP is one of the methods to find the optimum weight values with fault tolerance. But ILP has inability to solve the threshold functions with large inputs. This thesis presents two methods to overcome this difficulty.First one is the Combination method which combines the procedures of both decomposition method and ILP method .Second one is the Variable collapsing method which uses the principle of Variable Collapsing to find weights values with fault tolerance for large input functions.

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.

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Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-20T19:33:13Z No. of bitstreams: 1 CRISTOVÃO MÁCIO DE OLIVEIRA LIMA FILHO - DISSERTAÇÃO PPGEE 2010..pdf: 2095765 bytes, checksum: 1c2232fd0f1557df7308e04bad6426c2 (MD5) / Made available in DSpace on 2018-08-20T19:33:13Z (GMT). No. of bitstreams: 1 CRISTOVÃO MÁCIO DE OLIVEIRA LIMA FILHO - DISSERTAÇÃO PPGEE 2010..pdf: 2095765 bytes, checksum: 1c2232fd0f1557df7308e04bad6426c2 (MD5) Previous issue date: 2010-06-09 / Esta dissertação descreve o desenvolvimento de um leiaute de uma nova arquitetura de multiplicador em corpos finitos baseada no multiplicador de Mastrovito. Tal arquitetura tem como unidades de processamento as portas de limiar linear, que é o elemento básico de uma rede neural discreta. As redes neurais discretas implementadas com portas de limiar linear permitem reduzir a complexidade de certos circuitos antes implementados com lógica tradicional (Portas AND, OR e NOT). Com isso, a idéia de estender o uso de portas de limiar linear em operações aritméticas em corpos finitos se torna bastante atraente. Assim, para comprovar de forma prática, a eficiência das portas de limiar linear, a arquitetura de um multiplicador em GF(24), proposta em (LIDIANO - 2000), foi implementada utilizando as ferramentas de desenho de leiaute de circuito integrado da Mentor Graphics®. Os resultados da simulação do leiaute do circuito integrado do multiplicador em GF(24) são apresentados. Os mesmos indicaram um desempenho abaixo do esperado, devido a complexidade espacial do multiplicador em GF(2n) com 4=n não ser suficiente para que as vantagens da implementação com portas de limiar linear sejam visualizada. / This dissertation describes the development of a layout of new multiplication architecture in Galois field based on the Mastrovito multiplier. The processing unit of this new architecture is a threshold logic gate, which is a basic element of a discrete neural network. The discrete neural network built with threshold logic gates allow reduce de complexity of a certain circuits once built using traditional boolean gates (AND, OR and NOT). Therewith, the idea of extending the advantages of the threshold logic gates for arithmetic operations in Galois field to become very attractive. Thus, to confirm into practice form, the advantages of the threshold logic gates, a multiplier architecture in GF(24), proposed in (LIDIANO - 2000), was implemented using the integrated circuit layout tools of Mentor Graphics®. The results from simulations of the layout of multiplier in GF(24) are presented. These results indicated a low performance, due to the space complexity of GF(2n) multiplier with n = 4 is not enough for show the advantages of the multiplier implementation with threshold logic gates.