International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The UMR Solar Car uses a telemetry processor to collect, compute, and transmit data to the driver of the car and a nearby chase vehicle. The original processor had deteriorated from environmental extremes and vibration. There were also problems with electromagnetic interference from the high efficiency electric motor switching electronics, difficulties with the many unplanned additions made to the processor in the field, and the unstructured software that was becoming difficult to maintain. This project consists of creating a replacement telemetry system that is more robust mechanically, and electrically, substantially improving the EMI performance of the device, and reworking the hardware and software to make it easier to maintain and upgrade.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes the new Telemetry Processor Hardware (TPH) that Avtec Systems has developed for the Deep Space Network (DSN) Telemetry Processor (TLP) system. Avtec is providing the Telemetry Processor Hardware to RTLogic! for integration into the Telemetry Processor system. The Deep Space Network (DSN) is an international network of antennas that supports interplanetary spacecraft missions for exploration of the solar system and the universe. The Jet Propulsion Laboratory manages the DSN for NASA. The TLP system provides the capability to acquire, process, decode and distribute deep space probe and Earth orbiter telemetry data. The new TLP systems will be deployed at each of the three deep-space communications facilities placed approximately 120 degrees apart around the world: at Goldstone, California; near Madrid, Spain; and near Canberra, Australia. The Telemetry Processor Hardware (TPH) supports both CCSDS and TDM telemetry data formats. The TPH performs the following processing steps: soft-symbol input selection and measurement; convolutional decoding; routing to external decoders; time tagging; frame synchronization; derandomization; and Reed-Solomon decoding. The TPH consists of a VME Viterbi Decoder/MCD III Interface board (VM-7001) and a PCI-mezzanine Frame Synchronizer/Reed-Solomon Decoder (PMC- 6130-J) board. The new Telemetry Processor Hardware is implemented using the latest Field Programmable Gate Array (FPGA) technology to provide the density and speed to meet the current requirements as well as the flexibility to accommodate processing enhancements in the future.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes a PC-based Advanced Telemetry Processing and Display System (ATPDS)- a highend, real-time telemetry processing and display system implemented on a COTS PC platform. for A network-centric architecture was chosen from candidate architectures as the most viable for the ATPDS. The network-centric architecture is Windows NT-based, client/server based, supporting clients and servers on both local or remote PC workstations. The architecture supports distributing processing loads across multiple workstations, optimizing mission processing requirements. The advantage of this system is its flexibility and expandability with low acquisition and life-cycle support costs. The ATPDS allows the user to configure one or more small systems into a larger high-end system based on varying mission requirements.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / A system to generate a contiguous high speed time division multiplexed (TDM) spacecraft downlink data stream has been developed. The 25 MBPS downlink data stream contains high rate real time imager data, intermediate rate subsystem processor data, and low rate spacecraft housekeeping data. Imager data is transferred directly into the appropriate TDM downlink data window using control signals and clocks generated in the central data formatter and distributed to the data sources. Cable and electronics delays inherent in this process can amount to several clock periods, while the uncertainty and variations in those delays (e.g. temperature effects) can exceed the clock period. Unique (patent pending) electronic circuitry has been included in the data formatter to sense the total data gathering delay for each high speed data source and use the results to control series programmable delay elements to equalize the delays from all sources and permit the formation of a contiguous output data stream.