In this dissertation, advanced channel decoding techniques based on bit-level soft information are studied. Two main approaches are proposed: bit-level probabilistic iterative decoding and bit-level algebraic soft-decision (list) decoding (ASD). In the first part of the dissertation, we first study iterative decoding for high density parity check (HDPC) codes. An iterative decoding algorithm, which uses the sum product algorithm (SPA) in conjunction with a binary parity check matrix adapted in each decoding iteration according to the bit-level reliabilities is proposed. In contrast to the common belief that iterative decoding is not suitable for HDPC codes, this bit-level reliability based adaptation procedure is critical to the conver-gence behavior of iterative decoding for HDPC codes and it significantly improves the iterative decoding performance of Reed-Solomon (RS) codes, whose parity check matrices are in general not sparse. We also present another iterative decoding scheme for cyclic codes by randomly shifting the bit-level reliability values in each iteration. The random shift based adaptation can also prevent iterative decoding from getting stuck with a significant complexity reduction compared with the reliability based parity check matrix adaptation and still provides reasonable good performance for short-length cyclic codes. In the second part of the dissertation, we investigate ASD for RS codes using bit-level soft information. In particular, we show that by carefully incorporating bit¬level soft information in the multiplicity assignment and the interpolation step, ASD can significantly outperform conventional hard decision decoding (HDD) for RS codes with a very small amount of complexity, even though the kernel of ASD is operating at the symbol-level. More importantly, the performance of the proposed bit-level ASD can be tightly upper bounded for practical high rate RS codes, which is in general not possible for other popular ASD schemes. Bit-level soft-decision decoding (SDD) serves as an efficient way to exploit the potential gain of many classical codes, and also facilitates the corresponding per-formance analysis. The proposed bit-level SDD schemes are potential and feasible alternatives to conventional symbol-level HDD schemes in many communication sys-tems.

Programmers rely on programming idioms, design patterns, and workaround techniques to express fundamental design not directly supported by the language. Evolving languages often address frequently encountered problems by adding language and library support to subsequent releases. By using new features, programmers can express their intent more directly. As new concerns, such as parallelism or security, arise, early idioms and language facilities can become serious liabilities. Modern code sometimes bene fits from optimization techniques not feasible for code that uses less expressive constructs. Manual source code migration is expensive, time-consuming, and prone to errors. This dissertation discusses the introduction of new language features and libraries, exemplifi ed by open-methods and a non-blocking growable array library. We describe the relationship of open-methods to various alternative implementation techniques. The benefi ts of open-methods materialize in simpler code, better performance, and similar memory footprint when compared to using alternative implementation techniques. Based on these findings, we develop the notion of source code rejuvenation, the automated migration of legacy code. Source code rejuvenation leverages enhanced program language and library facilities by finding and replacing coding patterns that can be expressed through higher-level software abstractions. Raising the level of abstraction improves code quality by lowering software entropy. In conjunction with extensions to programming languages, source code rejuvenation o ers an evolutionary trajectory towards more reliable, more secure, and better performing code. We describe the tools that allow us efficient implementations of code rejuvenations. The Pivot source-to-source translation infrastructure and its traversal mechanism forms the core of our machinery. In order to free programmers from representation details, we use a light-weight pattern matching generator that turns a C like input language into pattern matching code. The generated code integrates seamlessly with the rest of the analysis framework. We utilize the framework to build analysis systems that find common workaround techniques for designated language extensions of C 0x (e.g., initializer lists). Moreover, we describe a novel system (TACE | template analysis and concept extraction) for the analysis of uninstantiated template code. Our tool automatically extracts requirements from the body of template functions. TACE helps programmers understand the requirements that their code de facto imposes on arguments and compare those de facto requirements to formal and informal specifications.

In Wideband DS-CDMA system, increasing the utilization of Orthogonal Variable Spreading Factor (OVSF) code tree can serve more users. As Dynamic Code Assignment (DCA) does, the allocated codes will be reassigned when a new call can¡¦t be served even if the capacity is enough. However, reassigning occupied codes is expensive. In this thesis, we have proposed a state classification code assignment principle and a proportional reservation policy. In the proposed algorithm, the OVSF code tree is classified into four states. Then, the system will decide whether to reassign codes or not by checking the current state of the tree. In other words, the occupied codes will be reallocated in an appropriate occasion. Besides, we reserve vacant and available codes corresponding to the probability of requests for each supported rate when reassignment occurs. Therefore, the reassignment is reduced. It is also proved on the basis of the property of Markov Chain. Taking advantage of the proposed states classification code assignment and the policy of proportional code reservation, the call blocking rate and the number of reassignment can be reduced.

Frequency reuse scheme is used to enhance the spectral efficiency in a cellular system, but inevitably the system suffers from co-channel interference of other users. Signal-to-interference ratio (SIR) is often used as a quality index of communication links. Several wireless communication algorithms, such as channel assignment, handover and power control, need real-time SIR information. All of these algorithms are under the assumptions that real-time SIR is available, but the methods of obtaining real-time SIR are seldom mentioned with these algorithms. In this thesis, we investigate three simple SIR estimation methods including statistics of spreading chips method, decorrelation detection method, and orthogonal stochastic approximation method. The performance of these SIR estimation methods are evaluated by computer simulations in a WCDMA system.

Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates. The design of the core SISO (Soft-In Soft-Out) unit used in Turbo Code decoder is based on the algorithm of SOVA (Soft-Output Viterbi Algorithm). Based on the hybrid trace-back scheme, the SISO proposed in this thesis can achieve fast path searching and path memory reduction which can be up to 70% compared with the traditional trace-back approach. In addition, every iterative of Turbo Code decoding performs two SISO operations on the block of data with normal and interleaving order. In our proposed architecture, these two SISO operations can be implemented on a single SISO unit with only slightly control overhead. In order to improve the bit error rate performance, the threshold and normalization techniques are applied to our design. In addition, the termination criteria circuit is also included in our design such that the iteration cycle of the decoding can be reduced. The proposed Turbo Code decoder has been thoroughly tested and verified, and can be qualified as a robust IP.

This thesis mainly focuses on the integration of Space-Time Block Coding (STBC) and Complementary Code based CDMA system. Our proposed integration systems have not only the merit of complementary code but also the extra advantage of diversity gain from STBC. Especially, when the different frequency channel gain has strong correlation, the complementary code will cancel most of interference. We also present a lot of improved structures for our proposed systems. We utilize special filters in receiver such as Zero-Forcing filter and Turbo Filter to assist complementary code in canceling interference.

This thesis mainly focuses on the integration of Space-Time Block Coding (STBC) and Complementary Code based CDMA system. Our proposed integration systems have not only the merit of complementary code but also the extra advantage of diversity gain from STBC. Especially, when the different frequency channel gain has strong correlation, the complementary code will cancel most of interference.

In this dissertation, we present mathematical analyses for a cellular CDMA communication system by investigating two important performance factors, the spreading code reservation periods and the cell coverage in soft handoff. First, an innovative code assignment scheme is presented by fully utilizing the characteristics of voice and data traffic. In other words, a voice terminal has higher priority to reserve a spreading code to transmit packets in multiple talk spurts, while a data terminal can only transmit packets by either employing the unassigned codes or borrowing the codes from the voice terminals during their silent periods. The code assignment scheme is then extended to analyze a priority-based CDMA system where the code reservation periods can be varied. Two performance measures, the average dropping probability for delay-sensitive traffic and the average packet delay for delay-insensitive traffic, are derived from the analytic models based on the equilibrium point analysis (EPA). Finally, for the cellular CDMA system, we study the influences of enlarging or shrinking the soft handoff coverage on the new-call blocking and the handoff-call dropping probabilities. From the mathematical analyses, we reveal that enlarging the outer cell while fixing the inner cell may significantly increase both blocking and dropping probabilities. On the other hand, if we enlarge the inner cell and fix the outer cell, the two probabilities can be reduced slightly. The impact of activating a call admission control on the proposed cellular CDMA system is also discussed.

When we survey hardware design groups, we can find that it is now dedicated to verification between 60 to 80 percent. According to the instruction set architecture information should be a feasible and reasonable way for generating the test pattern to verify the function of a microprocessor. In this these, we¡¦ll present an instruction test pattern (for microprocessors) generation method based on the instruction set architecture. It can help the users to generate the instruction test pattern efficiently. The generation flow in this thesis contains three major flows: individual instruction, instruction pair, and manual generation. They are used for different verification cases. The ¡§individual instruction¡¨ could be used for verifying the functions of each implemented instructions. The ¡§instruction pair¡¨ could be used for verifying the interaction of instruction execution in a pipeline for a HDL implementation of a microprocessor. The ¡§manual generation¡¨ could be used to verify some corner cases (behaviors) of the microprocessor. As the quality of our test pattern, we generate some patterns for 32-bits instruction (ARM instruction sets and SPARC instruction sets) and use them to verify a synthesizable RTL core. With some handwriting test pattern (34.7%), our automatic generation method can approach 100% HDL code coverage of the microprocessor design. We use the HDL code coverage as the reference of test pattern quality. Because our generation method is based on the instruction field, we can describe most instruction set for the generator. Hence, our generation method can retarget to most instruction set architecture without modifying the generator. Besides the RISC instructions, even the CISC instructions could be generated.

In embedded system, the system resource is limited. So, small is the most important feature of the embedded system. In this thesis, we propose a fast way to design a 16-bit microprocessor through reducing the 32-bit RISC CPU based on ARM 4vT Instruction set to the 16-bit RISC Thumb microprocessor. And through building the programming model, we can reach to save the design time of developing the compiler and assembler to keep its software environment.