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<p>Syftet med examensarbetet var att programmera en viterbiavkodare i VHDL och sedan syntetisera den till en FPGA. Först testades viterbialgoritmen i Matlab och Simulink för att få en förståelse för hur Viterbialgoritmen fungerar. Inom ramen för exjobbet har vi gjort en viterbiavkodare i Matlab samt en VHDL version som vi har simulerat i Modelsim. Avkodaren klarar inte av att avkoda punkterade bitströmmar. Att tillverka själva kodaren för punkterad kodning är enkelt men att sedan avkoda bitströmmen visade sig vara mer komplext. Att avkoda punkterad kod kräver ingen ändring av avkodaren men bitströmmen skall modifieras genom att man stoppar in dummybitar enligt ett givet mönster innan de når avkodaren men efter att mottagaren har tagit emot bitströmmen. Pga. tidsbrist prioriterades inte punkterad kodning och rapporten kom att ändra inriktning så att den snarare ska kunna fungera som starthjälp för kommande examensarbetare eller för andra inom universitetet som har till uppdrag att utveckla en viterbiavkodare.</p>

Syftet med examensarbetet var att programmera en viterbiavkodare i VHDL och sedan syntetisera den till en FPGA. Först testades viterbialgoritmen i Matlab och Simulink för att få en förståelse för hur Viterbialgoritmen fungerar. Inom ramen för exjobbet har vi gjort en viterbiavkodare i Matlab samt en VHDL version som vi har simulerat i Modelsim. Avkodaren klarar inte av att avkoda punkterade bitströmmar. Att tillverka själva kodaren för punkterad kodning är enkelt men att sedan avkoda bitströmmen visade sig vara mer komplext. Att avkoda punkterad kod kräver ingen ändring av avkodaren men bitströmmen skall modifieras genom att man stoppar in dummybitar enligt ett givet mönster innan de når avkodaren men efter att mottagaren har tagit emot bitströmmen. Pga. tidsbrist prioriterades inte punkterad kodning och rapporten kom att ändra inriktning så att den snarare ska kunna fungera som starthjälp för kommande examensarbetare eller för andra inom universitetet som har till uppdrag att utveckla en viterbiavkodare.

CPM advantageous in spectral efficiency because of its continuity of the phase in modulation. One of the CPM example is GMSK, which has been applied to the wireless GSM system. The conventional demodulaton og CPM is achieved by Viterbi algorithm. This is because of the state transition structure for the dynamic description of phase of the CPM signal. Furthermore, the state transition can be presented by a trellis diagram, which can be efficiently solved by Viterbi algorithm based upon the strategy of selecting best survivor path to a maximum likelihood criterion. The best survivor path is measured by the Euclidean distance in modulation in this thesis. Another demodulation method proposed by us is the famous BCJR algorithm. BCJR which is based upon the posteriori probabilities is a alternative method for decoding the convolution code. We compare the BCJR and Viterbi algorithm for the demodulation of the GMSK system. Experiment results demonstrate that BCJR has a better error probability than the Viterbi algorithm. Also, we compare different GMSK system for different overlapping length and modulation index. The best combination of L and h suggested by pur experiments is the case of L=3, and h=3/4.

A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM¡¦s with a length of T are applied for reducing the area of memory. The chip is implemented by TSMC standard 0.18-£gm 1P6M CMOS process with core area 1.061 ¡Ñ 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.

This thesis develops semi-automated methods to generate testbenches for VHDL models of communication systems. To illustrate the methods, a VHDL model was constructed for the speech-coding channel of the Global System for Mobile Communication (GSM). GSM is the Pan-European digital mobile telephony standard specified by the European Telecommunication Standards Institute (ETSI). This thesis emphasizes the error detection and error correction procedures that form an important part of the standard. First, a test bench template was generated using "Testbench Pro", a waveform generation tool developed by SynaptiCAD. The template includes a random sequence of speech data. A C program was then developed as a user interface to control the simulation procedure. Using the C program, the user can select a test bench template and specify the input test vectors. The C program adds the user's test vectors to the test bench template to create a final VHDL test bench that is ready for simulation. The testing data is then encoded by the GSM encoder models, passed through the noisy channel model that introduces errors into the data stream and, finally, passed through the GSM decoder models which attempt to correct the channel errors. Sophisticated error detection and error correction algorithms are used in the encoder/decoder models to increase the reliability of data transmission over the noisy channel. Finally, the original speech data is compared to the decoder output to detect any remaining bit errors and to evaluate the system performance. The simulation system is semi-automated. The user selects a set of parameters using the C program interface. A testbench is then automatically created and simulated. Two final report files are automatically generated. No user interaction is needed after the initial parameter selection. Several experiments were performed to illustrate the various features of the automated testbench generation system. / Master of Science

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The Viterbi algorithm has uses for both the decoding of convolutional codes and the detection of signals distorted by intersymbol interference (ISI). The operation of these processes is characterized by a trellis. An ARTM Tier-1 space-time coded telemetry receiver required the use of an irregular Viterbi trellis decoder to solve the dual antenna problem. The nature of the solution requires the trellis to deviate from conventional trellis structure and become time-varying. This paper explores the architectural challenges of such a trellis and presents a solution using a modified systolic array allowing the trellis to be realized in hardware.

This report details work completed on a subsection of a project to create a wireless transceiver for use with the TLL5000 Baseboards available in the University of Texas Embedded Microsystems Lab. The boards are used by students to learn about embedded systems and currently lack support for any wireless communications. As wireless communications are a vital part of many embedded systems, this project seeks to add wireless functionality. This report describes the work that has gone into the design of a transmission protocol, the implementation of a convolutional encoder and Viterbi decoder, and the writing of a driver to control the wireless hardware which will all run on the TLL-SILC 6219 ARM processor attached to the TLL5000 Baseboards. / text

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