Made available in DSpace on 2016-03-15T19:37:36Z (GMT). No. of bitstreams: 1 Marcos Almeida do Amaral.pdf: 924821 bytes, checksum: 9688a401b13ea6bec24b0af1024abf72 (MD5) Previous issue date: 2011-02-01 / Communications have achieved great development on several fronts over the years. Among these, the communication using chaotic signals has been object of growing interest among researchers due to the characteristics of spread spectrum and hard detection. However these techniques still have inferior performance in comparison to conventional methods in non-ideal channels. To contribute do the solution of this problem, statistical estimation algorithms have been applied to the detection of the transmitted signal. The objective of this thesis is to study a communication system using chaotic carriers and reception with maximum likelihood (ML-CSK - Maximum Likelihood Chaos Shift Keying). For this, the application of Viterbi algorithm in chaotic modulation signals is investigated. As the previously proposed algorithms offer only good performance to signals generated by maps that present well-behaved probability density, a new technique was designed based on analysis of the map characteristics, obtained numerically through a training vector. The results of performed simulations assure the applicability and the good performance of the proposed innovations. / As comunicações têm alcançado grande desenvolvimento em várias frentes ao longo dos anos. Dentre estas, a comunicação utilizando sinais caóticos vêm sendo objeto de crescente interesse por parte dos pesquisadores devido às características de espalhamento espectral e difícil detecção. Entretanto estas técnicas ainda apresentam um desempenho inferior em comparação com os métodos convencionais em canais não ideais. Para contornar este problema, algoritmos estatísticos de estimação vêm sendo aplicados na detecção dos sinais transmitidos. O objetivo desta dissertação é estudar um sistema de comunicação utilizando portadoras caóticas e recepção com máxima verossimilhança (ML-CSK - Maximum Likelihood Chaos Shift Keying). Para isto, a aplicação do algoritmo de Viterbi em sistemas de modulação por sinais caóticos é investigada. A partir da constatação de que os algoritmos propostos anteriormente só apresentam bom desempenho para sinais gerados por mapas que apresentam densidade de probabilidade bem comportada, uma nova técnica foi concebida baseada no levantamento das características do mapa, obtidas numericamente através de um vetor de treinamento. Os resultados das simulações executadas atestam a aplicabilidade e o bom desempenho das inovações propostas.

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / High data rate communication between airborne vehicles and ground stations over the bandwidth constrained Aeronautical Telemetry channel is attributed to the development of bandwidth efficient Advanced Range Telemetry (ARTM) waveforms. This communication takes place over a multipath channel consisting of two components - a line of sight and one or more ground reflected paths which result in frequency selective fading. We concentrate on the ARTM SOQPSKTG transmit waveform suite and decode information bits using the reduced complexity Viterbi algorithm. Two different methodologies are proposed to implement reduced complexity Viterbi decoders in multipath channels. The first method jointly equalizes the channel and decodes the information bits using the reduced complexity Viterbi algorithm while the second method utilizes the minimum mean square error equalizer prior to applying the Viterbi decoder. An extensive numerical study is performed in comparing the performance of the above methodologies. We also demonstrate the performance gain offered by our reduced complexity Viterbi decoders over the existing linear receiver. In the numerical study, both perfect and estimated channel state information are considered.

La correction d'erreur fera partie intégrante de toute technologie d'information quantique. Diverses méthodes de correction d'erreurs quantiques ont par conséquent été élaborées pour pallier les erreurs inévitables qui proviennent de la manipulation des qubits ainsi que de leur interaction inévitable avec l'environnement. Parmi les familles de codes de correction d'erreurs se trouvent les codes convolutifs, dont l'utilité envisagée est surtout pour protéger l'information quantique envoyée à travers un canal de communication bruyant. La méthode de décodage des codes convolutifs utilise des algorithmes d'estimation d'erreur basés sur un principe de maximum de vraisemblance. L'algorithme de Viterbi permet de déterminer ce maximum de vraisemblance de façon efficace. Cette méthode permet de trouver le mot code le plus probable et ce en utilisant des outils telle décodage par trellis. De plus, cet algorithme a une complexité linéaire avec le nombre de qubits encodés. Ce mémoire porte sur l'effet de la dégénérescence sur le décodage Viterbi. La dégénérescence est une propriété de lamécanique quantique ne possédant aucun analogue classique par laquelle des corrections distinctes peuvent corriger une erreur donnée. Les versions précédentes de décodage quantique suivant l'algorithme de Viterbi étaient sous-optimales parce qu'elles ne tenaient pas compte de la dégénérescence. La réalisation principale de ce mémoire est la conception d'un algorithme de décodage de Viterbi qui tient compte des erreurs dégénérées et nous les testons par des simulations numériques. Ces simulations démontrent qu'il y a effectivement un avantage à utiliser le décodeur Viterbi qui tient compte de la dégénérescence.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Gaussian Minimum Shift Keying (GMSK) is a form of Continuous Phase Modulation (CPM) whose spectral occupancy can be easily tailored to the available channel bandwidth by a suitable choice of signal parameters. The constant envelope of the GMSK signal enables it to corporate with saturated power amplifier without the spectral re-growth problem. This paper provides a quantitative synopsis of binary GMSK signals in terms of their bandwidth occupancy and coherent demodulation performance. A detailed account of how to demodulate such signals using the Viterbi Algorithm (VA) is given, along with analytical power spectral density (PSD) and computer simulated bit-error-rate (BER) results for various signal BT products. The effect of adjacent channel interference (ACI) is also quantified. Ideal synchronization for both symbol time and carrier phase is assumed.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes the new Telemetry Processor Hardware (TPH) that Avtec Systems has developed for the Deep Space Network (DSN) Telemetry Processor (TLP) system. Avtec is providing the Telemetry Processor Hardware to RTLogic! for integration into the Telemetry Processor system. The Deep Space Network (DSN) is an international network of antennas that supports interplanetary spacecraft missions for exploration of the solar system and the universe. The Jet Propulsion Laboratory manages the DSN for NASA. The TLP system provides the capability to acquire, process, decode and distribute deep space probe and Earth orbiter telemetry data. The new TLP systems will be deployed at each of the three deep-space communications facilities placed approximately 120 degrees apart around the world: at Goldstone, California; near Madrid, Spain; and near Canberra, Australia. The Telemetry Processor Hardware (TPH) supports both CCSDS and TDM telemetry data formats. The TPH performs the following processing steps: soft-symbol input selection and measurement; convolutional decoding; routing to external decoders; time tagging; frame synchronization; derandomization; and Reed-Solomon decoding. The TPH consists of a VME Viterbi Decoder/MCD III Interface board (VM-7001) and a PCI-mezzanine Frame Synchronizer/Reed-Solomon Decoder (PMC- 6130-J) board. The new Telemetry Processor Hardware is implemented using the latest Field Programmable Gate Array (FPGA) technology to provide the density and speed to meet the current requirements as well as the flexibility to accommodate processing enhancements in the future.

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / A new class of non-coherent detection techniques for recently standardized Feher patented quadrature phase-shift keying (FQPSK) systems is proposed and studied by computer aided design/simulations and also verified by experimental hardware measurements. The theoretical concepts of the described non-coherent techniques are based on an interpretation of the instantaneous frequency deviation or phase transition characteristics of FQPSK-B modulated signal at the front end of the receiver. These are accomplished either by Limiter-Discriminator (LD) or by Limiter-Discriminator followed by Integrate-and-Dump (LD I&D) methods. It is shown that significant BER performance improvements can be obtained by increasing the received signal’s observation time over multiple symbols as well as by adopting trellis-demodulation. For example, our simulation results show that a BER=10^-4 can be obtained for an E(b)/N(0)=12.7 dB.

Since the invention of wireless telegraphy by Marconi in 1897, wireless technology has not only been enhanced, but also has become an integral part of our everyday lives. The first wireless mobile phone appeared around 1980. It was based on first generation analog technology that involved the use of Frequency Division Multiple Access (FDMA) techniques. Ten years later, second generation (2G) mobiles were dependent on Time Division Multiple Access (TDMA) techniques and Code Division Multiple Access (CDMA) techniques. Nowadays, third generation (3G) mobile systems depend on CDMA techniques to satisfy the need for faster, and more capacious data transmission in mobile wireless networks. Wideband CDMA (WCDMA) has become the major 3G air interface in the world. WCDMA employs convolutional encoding to encode voice and MPEG4 applications in the baseband transmitter at a maximum frequency of 2<i>Mbps</i>. To decode convolutional codes, Andrew Viterbi invented the Viterbi Decoder (VD) in 1967. In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. Conceptually, the Register Exchange (RE) method is simpler and faster than the Trace Back (TB) method for implementing the VD. However, in the RE method, each bit in the memory must be read and rewritten for each bit of information that is decoded. Therefore, the RE method is not appropriate for decoders with long constraint lengths. Although researchers have focused on implementing and optimizing the TB method, the RE method is focused on and modified in this thesis to reduce the RE method's power consumption. This thesis proposes a novel modified RE method by adopting a <i>pointer</i> concept for implementing the survivor memory unit (SMU) of the VD. A pointer is assigned to each register or memory location. The contents of thepointer which points to one register is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE's SMU implementation (modified RE), there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA systems require 256 rows of memory. Applying the pointer concept reduces the VD's power consumption by 20 percent as estimated by the VHDL synthesis tool and by the new power reduction estimation that is introduced in this work. The coding gain for the modified RE method is 2. 6<i>dB</i> at an SNR of approximately 10-3. Furthermore, a novel zero-memory implementation for the modified RE method is proposed. If the initial state of the convolutional encoder is known, the entire SMU of the modified RE VD is reduced to only one row. Because the decoded data is generated in the required order, even this row of memory is dispensable. The zero-memory architecture is called the MemoryLess Viterbi Decoder (MLVD), and reduces the power consumption by approximately 50 percent. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 <i>MHz</i> with a decoding throughput of more than 3<i>Mbps</i> and a latency of two data bits. The other problem of the VD which is addressed in this thesis is the Add Compare Select Unit (ACSU) which is composed of 128 butterfly ACS modules. The ACSU's high parallelism has been previously solved by using a bit serial implementation. The 8-bit First Input First Output (FIFO) register, needed for the storage of each path metric (PM), is at the heart of the single bit serial ACS butterfly module. A new, simply controlled shift register is designed at the circuit level and integrated into the ACS module. A chip for the new module is also fabricated.

As the demands of communication systems have become more complex and varied, software defined radios (SDR) have become increasingly popular. With behavior that can be modified in software, SDR's provide a highly flexible and configurable development environment. Despite its programmable behavior, the maximum performance of an SDR is still rooted in its hardware. This limitation and the desire for the use of SDRs in different applications have led to the rise of various pieces of hardware to serve as SDR platforms. These platforms vary in aspects such as their performance limitations, implementation details, and cost. In this way the choice of SDR platform is not solely based on the cost of the hardware and should be closely examined before making a final decision. This thesis examines the various SDR platform families available on the market today and compares the advantages and disadvantages present for each during development. As many different types of hardware can be considered an option to successfully implement an SDR, this thesis specifically focuses on general purpose processors, system on chip, and field-programmable gate array implementations. When examining these SDR families, the Freescale BSC9131 is chosen to represent the system on chip implementation, while the Nutaq PicoSDR 2x2 Embedded with Virtex6 SX315 is used for the remaining two options. In order to test each of these platforms, a Viterbi algorithm is implemented on each and the performance measured. This performance measurement considers both how quickly the platform is able to perform the decoding, as well as its bit error rate performance in order to ascertain the implementations' accuracy. Other factors considered when comparing each platform are its flexibility and the amount of options available for development. After testing, the details of each implementation are discussed and guidelines for choosing a platform are suggested.

Optimal decision directed equalization techniques for time dispersive communication channels are often too complex to implement. This thesis considers reduced complexity decision directed equalization that lowers complexity demands yet retains close to optimal performance. The first part of this dissertation consists of three reduced complexity algorithms based on the Viterbi Algorithm (VA) which are: the Parallel Trellis VA (PTVA); Time Reverse Reduced State Sequence Estimation (TR-RSSE); and Forward-Backward State Sequence Detection (FBSSD). The second part of the thesis considers structural modifications of the Decision Feedback Equalizer (DFE), which is a special derivative of the VA, specifically, optimal vector quantization for fractionally spaced DFEs, and extended stability regions for baud spaced DFEs using passivity analysis are investigated.¶ For a special class of sparse channels the VA can be decomposed over a number of independent parallel trellises. This decomposition will be called the Parallel Trellis Viterbi Algorithm and can have lower complexity than the VA yet it retains optimal performance. By relaxing strict sparseness constraints on the channel a sub-optimal approach is proposed which keeps complexity low and obtains good performance.¶ Reduced State Sequence Estimation (RSSE) is a popular technique to reduce complexity. However, its deficiency can be the inability to adequately equalize non-minimum phase channels. For channels that have energy peaks in the tail of the impulse response (post-cursor dominant) RSSE's complexity must be close to the VA or performance will be poor. Using a property of the VA which makes it invariant to channel reversal, TR-RSSE is proposed to extend application of RSSE to post-cursor dominant channels.¶ To further extend the class of channels suitable for RSSE type processing, FBSSD is suggested. This uses a two pass processing method, and is suited to channels that have low energy pre and post-cursor. The first pass generates preliminary estimates used in the second pass to aid the decision process. FBSSD can range from RSSE to TR-RSSE depending on parameter settings.¶ The DFE is obtained when the complexity of RSSE is minimized. Two characterizing properties of the DFE, which are addressed in this thesis, are feedback and quantization. A novel fractionally spaced (FS) DFE structure is presented which allows the quantizer to be generalized relative to the quantizer used in conventional FS-DFEs. The quantizer can be designed according to a maximum a posteriori criterion which takes into account a priori statistical knowledge of error occurrences. A radically different quantizer can be obtained using this technique which can result in significant performance improvements.¶ Due to the feedback nature of the DFE a form of stability can be considered. After a decision error occurs, a stable DFE will, after some finite time and in the absence of noise, operate error free. Passivity analysis provides sufficient conditions to determine a class of channels which insures a DFE will be stable. Under conditions of short channels and small modulation alphabets, it is proposed that conventional passivity analysis can be extended to account for varying operator gains, leading to weaker sufficient conditions for stability (larger class of channels).

Dans cette thèse nous proposons une nouvelle approche dans le cadre des modèles d'évaluation des actifs financiers permettant de tenir compte de deux aspects fondamentaux qui caractérisent la volatilité latente: co-mouvement des rendements financiers conditionnellement hétéroscédastiques et changement de régime. En combinant les modèles à facteurs conditionnellement hétéroscédastiques avec les modèles de chaîne de Markov cachés, nous dérivons un modèle multivarié localement linéaire et dynamique pour la segmentation et la prévision des séries financières. Nous considérons, plus précisément le cas où les facteurs communs suivent des processus GQARCH univariés. L'algorithme EM que nous avons développé pour l'estimation de maximum de vraisemblance et l'inférence des structures cachées est basé sur une version quasi-optimale du filtre de Kalman combinée avec une approximation de Viterbi. Les résultats obtenus sur des simulations, aussi bien que sur des séries financières sont prometteurs.