Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates. The design of the core SISO (Soft-In Soft-Out) unit used in Turbo Code decoder is based on the algorithm of SOVA (Soft-Output Viterbi Algorithm). Based on the hybrid trace-back scheme, the SISO proposed in this thesis can achieve fast path searching and path memory reduction which can be up to 70% compared with the traditional trace-back approach. In addition, every iterative of Turbo Code decoding performs two SISO operations on the block of data with normal and interleaving order. In our proposed architecture, these two SISO operations can be implemented on a single SISO unit with only slightly control overhead. In order to improve the bit error rate performance, the threshold and normalization techniques are applied to our design. In addition, the termination criteria circuit is also included in our design such that the iteration cycle of the decoding can be reduced. The proposed Turbo Code decoder has been thoroughly tested and verified, and can be qualified as a robust IP.

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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / With the characteristics of constant envelope and continuous phase, Continuous Phase Modulation (CPM) signal has higher spectrum efficiency and power efficiency than other modulation forms. A noncoherent demodulation with Viterbi decoding for partial response CPM signals is proposed. Simulation results indicate that the demodulation performance of proper partial response CPM is better than the traditional PCM-FM, which is a typical modulation of full response CPM. And higher spectral efficiency is also obtained by partial response CPM.

Τα τελευταία χρόνια ο όγκος των δεδομένων που διακινείται μέσω δικτυακών συστημάτων είναι συνεχώς αυξανόμενος με την επιτακτική ανάγκη για αξιόπιστη επικοινωνία. Παρόλο που η εξέλιξη της τεχνολογίας επιτρέπει μεγαλύτερη ανοχή σε παρεμβολές στο τηλεπικοινωνιακό κανάλι, ο υψηλότερος ρυθμός δεδομένων προκαλεί παραμορφώσεις στο σήμα και κάνει το τηλεπικοινωνιακό σύστημα πιο επιρρεπές στον θόρυβο. Παράδειγμα τέτοιων συστημάτων αποτελούν εφαρμογές ασύρματων δικτύων όπως τα συστήματα κινητής τηλεφωνίας, οι δορυφορικές επικοινωνίες, ασύρματα τοπικά δίκτυα WiFi καθώς και ενσύρματων επικοινωνιών (ενσύρματα Modem). Η παρούσα διπλωματική επικεντρώνεται στα πρότυπα 802.11 που αφορούν ασύρματα τοπικά δίκτυα και πιο συγκεκριμένα στο πρόσφατο 802.11ac ώστε να τεθούν συγκεκριμένα κριτήρια απόδοσης. Αφενός γίνεται σχεδιασμός και υλοποίηση ενός αποκωδικοποιητή σύμφωνου με το πρότυπο λαμβάνοντας υπόψη περιορισμούς χρονισμού αλλά και επιφάνειας και επαλήθευση αυτών μέσω τεχνολογιών FPGA και ASIC. Αφετέρου μελετώνται διαφορετικές αρχιτεκτονικές υλοποίησης του αλγορίθμου (πχ high radix) και εξετάζονται τα πιθανά σχεδιαστικά trade-off. Εξετάζονται μέθοδοι αύξησης του throughput αλλά και θέματα απόδοσης που αφορούν την ικανότητα διόρθωσης λαθών. / In recent years the volume of data handled by network systems is growing with the need for reliable communication . Although the evolution of technology allows greater tolerance to interference in the telecommunication channel , higher data rate causes distortion to the signal and makes the telecommunication system more susceptible to noise. Examples of such systems are applications of wireless networks such as cellular systems , satellite communications , wireless local area networks WiFi and wired communications ( wired Modem). This thesis focuses on the 802.11 standards regarding wireless LANs and in particular in recent 802.11ac to put specific performance criteria. First is design and implementation of a decoder conforming to the model taking into account timing and surface constraints and verification technologies through FPGA and ASIC. Secondly, different architectures of the algorithm ( eg high radix) are studied and the possible design trade-off is examined. Methods of increasing the throughput and performance issues relating to error correction capability are examined.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

No description available.

No description available.

Les équipements de communications numériques intègrent de plus en plus de standards. La commutation d’un standard à l’autre doit pouvoir se faire au prix d’un surcoût matériel modéré, ce qui impose l’utilisation de ressources communes dans des instanciations différentes. La plateforme matérielle nécessaire à l’exécution d’une couche physique multistandard est le segment du système présentant le plus de contraintes par rapport à la reconfiguration : réactivité, consommation et occupation de ressources matérielles. Nos travaux se focalisent sur la paramétrisation qui vise une implémentation multistandards efficace. L’objectif de cette technique est d’identifier des traitements communs entre les standards, voire entre blocs de traitement au sein d’un même standard, afin de définir des blocs génériques pouvant être réutilisés facilement. Nous définissons le management d’opérateurs mutualisés (opérateurs communs) et nous étudions leur implémentation en se basant essentiellement sur des évaluations de complexité pour quelques standards utilisant la modulation OFDM. Nous proposons en particulier l’architecture d’un opérateur commun permettant la gestion efficace des ressources matérielles entre les algorithmes FFT et décodage de Viterbi. L’architecture, que nous avons proposé et implémenté sur FPGA, permet d’adapter le nombre d’opérateurs communs alloués à chaque algorithme et donc permet l’accélération des traitements. Les résultats montrent que l’utilisation de cette architecture commune offre des gains en complexité pouvant atteindre 30% dans les configurations testées par rapport à une implémentation classique avec une réduction importante de l’occupation mémoire. / Today's telecommunication systems require more and more flexibility, and reconfiguration mechanisms are becoming major topics especially when it comes to multistandard designs. In typical hardware designs, the communication standards are implemented separately using dedicated instantiations which are difficult to upgrade for the support of new features. To overcome these issues, we exploit a parameterization approach called the Common Operator (CO) technique that can be considered to build a generic terminal capable of supporting a large range of communication standards. The main principle of the CO technique is to identify common elements based on smaller structures that could be widely reused across signal processing functions. This technique aims at designing a scalable digital signal processing platform based on medium granularity operators, larger than basic logic cells and smaller than signal processing functions. In this thesis, the CO technique is applied to two widely used algorithms in wireless communication systems: Viterbi decoding and Fast Fourier Transform (FFT). Implementing the FFT and Viterbi algorithms in a multistandard context through a common architecture poses significant architectural constraints. Thus, we focus on the design of a flexible processor to manage the COs and take advantage from structural similarities between FFT and Viterbi trellis. A flexible FFT/Viterbi processor was proposed and implemented on FPGA and compared to dedicated hardware implementations. The results show a considerable gain in flexibility. This gain is achieved with no complexity overhead since the complexity if even decreased up to 30% in the considered configurations.