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Convolutional code design and performanceLee, L. H. C. January 1987 (has links)
No description available.
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RTL implementation of Viterbi DecoderChen, Wei January 2006 (has links)
<p>A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University.</p><p>In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance.</p><p>The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.</p>
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Viterbi Decoding for OFDM systems operating in narrow band interferenceMukherjee, Arijit 28 September 2009 (has links)
Our main objective in this thesis is to study the effect of narrow band interference on OFDM systems operating in the 2.4 Ghz ISM band and identify ways to improve upon existing techniques to deal with them. We first consider how narrow band signals interfere with OFDM systems. Various noise variance estimation and signal to noise ratio estimation techniques for OFDM systems are then discussed. We also study the conventional Viterbi Algorithm that is used in OFDM wireless systems and the proposed modifications to it in the literature. Our main contribution is a detailed experimental analysis of a modified Viterbi Algorithm that outperforms the conventional one in the presence of narrow band interference. Interference samples captured using a wireless hardware platform were used in simulation to test this modified algorithm. From our analysis we realize that in the presence of narrow band frequency selective interference (such as Bluetooth), the conventional Viterbi Algorithm can be modified to improve the performance of OFDM systems.
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Viterbi Decoding for OFDM systems operating in narrow band interferenceMukherjee, Arijit 28 September 2009 (has links)
Our main objective in this thesis is to study the effect of narrow band interference on OFDM systems operating in the 2.4 Ghz ISM band and identify ways to improve upon existing techniques to deal with them. We first consider how narrow band signals interfere with OFDM systems. Various noise variance estimation and signal to noise ratio estimation techniques for OFDM systems are then discussed. We also study the conventional Viterbi Algorithm that is used in OFDM wireless systems and the proposed modifications to it in the literature. Our main contribution is a detailed experimental analysis of a modified Viterbi Algorithm that outperforms the conventional one in the presence of narrow band interference. Interference samples captured using a wireless hardware platform were used in simulation to test this modified algorithm. From our analysis we realize that in the presence of narrow band frequency selective interference (such as Bluetooth), the conventional Viterbi Algorithm can be modified to improve the performance of OFDM systems.
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RTL implementation of Viterbi DecoderChen, Wei January 2006 (has links)
A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University. In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance. The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.
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Implementation of a Forward Error Correction Technique using Convolutional Encoding with Viterbi DecodingRawat, Sachin 30 June 2004 (has links)
No description available.
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Software implementation of Viterbi maximum-likelihood decodingAlmonte, Caonabo January 1981 (has links)
No description available.
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Noncoherent Demodulation with Viterbi Decoding for Partial Response Continuous Phase ModulationXingwen, Ding, Yumin, Zhong, Hongyu, Chang, Ming, Chen 10 1900 (has links)
ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / With the characteristics of constant envelope and continuous phase, Continuous Phase Modulation (CPM) signal has higher spectrum efficiency and power efficiency than other modulation forms. A noncoherent demodulation with Viterbi decoding for partial response CPM signals is proposed. Simulation results indicate that the demodulation performance of proper partial response CPM is better than the traditional PCM-FM, which is a typical modulation of full response CPM. And higher spectral efficiency is also obtained by partial response CPM.
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MODIFIED VITERBI DECODING ALGORITHM FOR CIRCULAR TRELLIS-CODED MODULATIONCui, Xiaoxiao January 2000 (has links)
No description available.
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Downlink W-CDMA performance analysis and receiver implmentation on SC140 Motorola DSPGhosh, Kaushik 30 September 2004 (has links)
High data rate applications are the trend in today's wireless technology. W-CDMA standard was designed to support such high data rates of up to 3.84 Mcps. The main purpose of this research was to analyze the feasibility of a fixed-point implementation of the W-CDMA downlink receiver algorithm on a general-purpose digital signal processor (StarCore SC140 by Motorola). The very large instruction word architecture of SC140 core is utilized to generate optimal implementation, to meet the real time timing requirements of the algorithm. The other main aim of this work was to study and evaluate the performance of the W-CDMA downlink structure with incorporated space-time transmit diversity. The effect of the channel estimation algorithm used was extensively studied too.
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