This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags. OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.

Nanocrystalline silicon (nc-Si:H) is a promising material for Thin-Film Transistors (TFTs) offering potentially higher mobilities and improved stability over hydrogenated amorphous silicon (a-Si:H). The slow growth rate of nc-Si:H can be overcome by using pulsed Plasma-Enhanced Chemical Vapour Deposition (PECVD). Pulsed PECVD also reduces powder particle formation in the plasma and provides added degrees of freedom for process optimization. Unlike high frequency PECVD, pulsed PECVD can be scaled to deposit films over large areas with no reduction in performance. For this thesis, silicon thin films were deposited by the pulsed PECVD technique at a temperature of 150 °C and TFTs were made using this material. Radio Frequency (RF) power and silane (SiH₄) flow rate were varied in order to study the effect of different levels of crystallinity on the film. Raman spectroscopy, Atomic Force Microscope (AFM), X-Ray Diffraction (XRD), electrical conductivity, Hall mobility, optical band gap, and stability under light-soaking were measured using films of two different thicknesses, 50 nm and 300 nm. From the Raman data we see that the 50 nm films deposited with high hydrogen dilution are mostly amorphous, indicating the presence of a thick incubation layer. The 300nm samples deposited with hydrogen dilution, on the other hand, showed very high crystallinity and conductivity, except for 300-2 which was surprisingly, mostly amorphous. AFM and XRD measurements were also performed to confirm the Raman data and get an estimate for the crystallite grain size in the 300 nm samples. The conductivity was measured for all films, and the Hall mobility and carrier concentration was measured for one of the 300 nm films. The thin samples which are mostly amorphous show low conductivity whereas the thick high crystallinity films show high conductivity, and n-type behaviour possibly due to oxygen doping. The optical gap was also measured using Ultra Violet (UV) light and results indicate the possible presence of small crystallites in the 50 nm films. The conductivity's stability under light-soaking was measured to observe the material's susceptibility to degradation, and the 300 nm with high crystallinity were much more stable than the a-Si:H films. All the results of these measurements varied depending on the film and these results are discussed. Bottom-gate TFTs were fabricated using a pulsed PECVD channel layer and an amorphous silicon nitride (a-SiN:H) gate dielectric. The extracted parameters of one of the best TFTs are <i>&mu;_sat</i> &le; 0. 38 cm² V^-1 s^-1, <i>V_t,sat</i> &ge; 7. 3 V, <i>I_on/off</i> > 10⁶, and <i>S</i> < 1 V/decade. These parameters were extracted semi-automatically from the basic Field-Effect Transistor (FET) model using a computer program. Extraction using a more complicated model yielded similar results for mobility and threshold voltage but also gave a large power parameter <i>&alpha;</i> of 2. 31 and conduction band tail slope of 30 meV. The TFT performance and material properties are presented and discussed. On this first attempt at fabricating TFTs using a nc-Si:H channel layer deposited by pulsed PECVD, results were obtained which are consistent with results for low temperature a-Si:H TFTs and previous pulsed PECVD TFTs. The channel layer was mostly amorphous and non-crystalline, possibly due to the amorphous substrate or insufficient hydrogen dilution in the plasma. The 300 nm films showed, however, that high crystallinity material deposited directly on glass can easily be obtained, and this material showed less degradation under light-soaking than the purely amorphous counterpart. Pulsed PECVD is a promising technique for the growth of nc-Si:H and with further materials development and process optimization for TFTs, it may prove to be useful for the growth of high-quality nc-Si:H TFT channel layers.

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags. OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

In this dissertation, the electrical characteristics of generally used hydrogenated amorphous silicon (a-Si:H) TFTs in LCD and newly risen amorphous indium-gallium-zinc oxide (a-IGZO) TFTs were studied. For modern mobile display and large-size flat panel display application, the traditional thin-film transistor-liquid crystal display (TFT-LCD) technology confronts with a lot of challenges and problems. In general, flexible displays must exhibit some bending ability; however, bending applies mechanical strain to electronic circuits and affects device characteristics. Therefore, the electrical characteristics of a-Si:H TFTs fabricated on stainless steel foil substrates with uniaxial bending were investigated at different temperatures. Experimental results showed that the on-state current and threshold voltage degraded under outward bending. This is because outward bending will induce the increase of band tail states, affecting the transport mechanism at different temperatures. In addition, for practical operation, the electrical characteristics of a-Si:H TFTs under flat and bending situations after AC/DC stress at different temperatures were studied. It was found that high temperature and mechanical bending played important roles under AC stress. The dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress was also observed. Because a-Si:H is a photosensitive material, the high intensity backlight illumination will degrade the performance of a-Si:H TFTs. Thus, the photo-leakage current of a-Si:H TFTs under illumination was investigated at different temperatures. Experimental results showed that a-Si:H TFTs exhibited a pool performance at lower temperatures. The indirect recombination rate and the parasitic resistance (Rp) are responsible for the different photo-leakage-current trends of a-Si:H TFTs under varied temperature operations. To investigate the photo-leakage current, the a-Si:H TFTs were exposed to ultraviolet (UV) light irradiation. It was found that the photo current of a-Si:H TFTs was reduced after UV light irradiation. The detail mechanisms on reducing/increasing photo-leakage current by UV light irradiation were discussed. Recently, the oxide-based semiconductor TFT, especially a-IGZO TFT, is considered as one of promising candidates for active matrix flat-panel display. However, the a-IGZO TFT exists significant electrical instability issue and manufacturing problems. As a consequence, we investigated the effect of hydrogen incorporation on a-IGZO TFTs to reduce interface states between active layer and insulator. Experimental results showed that the electrical characteristics of hydrogen-incorporated a-IGZO TFTs were improved. The threshold voltage shift (£GVth) in hysteresis loop is suppressed from 4 V to 2 V due to the hydrogen-induced passivation of the interface trap states. Finally, we reported the effect of ambient environment on a-IGZO TFT instability. As a-IGZO TFTs were stored in atmosphere environment for 40 days, the transfer characteristics accompanying strange hump were observed during bias-stress. The hump phenomenon is attributed to the absorption of H2O molecule. Additionally, the sufficient electric field is also necessary to cause this anomalous transfer characteristic.

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

CdSe thin films were deposited by thermal evaporation and e-beam evaporation techniques on to well cleaned glass substrates. Low dose of boron have been implanted on a group of samples. EDAX and X-ray patterns revealed that almost stoichiometric polycrystalline films have been deposited in (002) preferred orientation. An analysis of optical measurements revealed a sharp increase in absorption coefficient below 700 nm and existence of a direct allowed transition. The calculated band gap was around 1.7 eV. The room temperature conductivity values of the samples were found to be between 9.4 and 7.5x10-4 (&amp / #937 / -cm)-1 and 1.6x10-6 and 5.7x10-7 (&amp / #937 / -cm)-1for the thermally evaporated and e-beam evaporated samples respectively. After B implantation conductivity of these films increased 5 and 8 times respectively. Hall mobility measurements could be performed only on the thermally evaporated and B-implanted e-beam evaporated samples and found to be between 8.8 and 86.8 (cm2/V.s). The dominant conduction mechanism were determined to be thermionic emission above 250 K for all samples. Tunneling and v variable range hopping mechanisms have been observed between 150-240 K and 80- 140 K respectively. Photoconductivity &amp / #8211 / illumination intensity plots indicated two recombination centers dominating at the low and high regions of studied temperature range of 80-400 K. Photoresponse measurements have corrected optical band gap measurements by giving peak value at 1.72 eV.

In order to improve the efficiency of various optical surfaces, optical coatings are used. Optical coating is a process of depositing a thin layer of a material on an optical component such as mirror or lens to change reflectance or transmittance. There are two main types of coatings namely / reflective and antireflective (AR) Coatings. Reflective and antireflective coatings have long been developed for a variety of applications in all aspects of use / for optical and electro-optical systems in telecommunications, medicine, military products and space applications. In this thesis, the main properties of reflective and antireflective coatings, the thin film deposition techniques, suitable coating materials for space applications, space environment effects on coating materials and coating design examples which are developed using MATLAB for space applications will be discussed.