Η διπλωματική εργασία υλοποιεί και προσομοιώνει αλγόριθμο για τη βέλτιστη διαχείριση φορητών συσκευών σε ετερογενή ασύρματα δίκτυα. Στο πρώτο κεφάλαιο γίνεται μια εισαγωγή στις γενικές αρχές των Κυτταρικών Συστημάτων Κινητών Επικοινωνιών παρουσιάζοντας την βασική ιδέα των διαφόρων γενιών κινητών επικοινωνιών. Στο δεύτερο κεφάλαιο αναλύονται τα συστήματα τρίτης γενιάς – 3G. Στο τρίτο κεφάλαιο αναφέρονται τα τεχνικά χαρακτηριστικά, τα πλεονεκτήματα και οι σχέσεις της πλατφόρμας TETRA. Στο τέταρτο κεφάλαιο περιγράφεται το σύστημα και οι λειτουργίες του TETRAPOL καθώς και τα πλεονεκτήματα και οι υπηρεσίες που προσφέρει αυτό. Στο 5ο κεφάλαιο αναλύονται τα συστατικά οι υπηρεσίες και οι λειτουργίες του iDen. Στο κεφάλαιο 6 γίνεται μια αναφορά στο πρωτόκολλο WiMax. Στα κεφάλαια 7 & 8 παρουσιάζονται ο αλγόριθμος της διαχείρισης συσκευών και η εξομοίωσή του σε MATLAB. / -

Nowadays, Third Generation (3G) mobile phones equipped with powerful hardware are becoming popular and dominating the market of cellular com-munication systems. Features such as music and video players, in-built Global Positioning System (GPS) receivers, navigation maps, Internet connectivity and high resolution cameras has converted mobile phones into so called Smartphones. With the increase in applications and services, limitations on energy consumption are also increasing. Therefore, it is more im-portant for manufacturers to nd e ective means of increasing battery life of mobile phones, as the mobile device itself is energy consuming and longer operational times are demanded by customers. Good energy mangement in mobile phones requires a good understanding of the energy usage in mobile phones. To this end, this thesis report presents the results of power and energy consumption measurements conducted on available Smartphones. The services under investigation includes basic Smartphone functionalities and few Internet services are studied and conclusions were drawn. This paper presents a cost e ective methodology for reliable measurements of energy on Smartphones. It also examines the e ect of operating systems on en-ergy consumption in mobile phones and reports less energy consumption for Android supported phones. The energy consumption of these Smartphones with respect to various applications has been studied and related to Quality of Experience of users'. Based on the results conclusions were drawn. / This Thesis will serve as a guide to manufacturers and Users of smartphones while choosing smartphones and designing energy-efficient protocols. / +46 (0)723260656

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.