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Efficient Conditional Synchronization for Transactional Memory Based SystemNaik, Aniket Dilip 10 April 2006 (has links)
Multi-threaded applications are needed to realize the full potential
of new chip-multi-threaded machines. Such applications are
very difficult to program and orchestrate correctly, and transactional
memory has been proposed as a way of alleviating some of the programming
difficulties. However, transactional memory can directly
be applied only to critical sections, while conditional synchronization
remains difficult to implement correctly and efficiently.
This dissertation describes EasySync, a simple and inexpensive extension
to transactional memory that allows arbitrary conditional
synchronization to be expressed in a simple and composable way.
Transactional memory eliminates the need to use locks and provides
composability for critical sections: atomicity of a transaction is
guaranteed regardless of how other code is written. EasySync provides
the same benefits for conditional synchronizations: it eliminates
the need to use conditional variables, and it guarantees wakeup
of the waiting transaction when the real condition it is waiting for
is satisfied, regardless of whether other code correctly signals that
change. EasySync also allows transactional memory systems to efficiently
provide lock-free and condition variable-free conditional
critical regions and even more advanced synchronization primitives,
such as guarded execution with arbitrary conditional or guard code.
Because EasySync informs the hardware the that a thread is
waiting, it allows simple and effective optimizations, such as stopping
the execution of a thread until there is a change in the condition
it is waiting for. Like transactional memory, EasySync is backward compatible
with existing code, which we confirm by running unmodified
Splash-2 applications linked with an EasySync-based synchronization
library. We also re-write some of the synchronization
in three Splash-2 applications, to take advantage of better code readability,
and to replace spin-waiting with its more efficient EasySync
equivalents.
Our experimental evaluation shows that EasySync successfully
eliminates processor activity while waiting, reducing the number of
executed instructions by 8.6% on average in a 16-processor CMP.
We also show that these savings increase with the number of processors,
and also for applications written for transactional memory
systems. Finally, EasySync imposes virtually no performance overheads,
and can in fact improve performance.
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DLL-Conscious Instruction Fetch Optimization for SMT ProcessorsMohamood, Fayez 12 April 2006 (has links)
Simultaneous multithreading (SMT) processors can issue multiple instructions from distinct processes or threads in the same cycle. This technique effectively increases the overall throughput by keeping the pipeline resources more occupied at the potential expense of reducing single thread performance due to resource sharing. In the software domain, an increasing number of Dynamically Linked Libraries (DLL) are used by applications and
operating systems, providing better flexibility and modularity, and enabling code sharing. It is observed that a significant amount of execution time in software today is spent in executing standard DLL instructions, that are shared among multiple threads or processes. However, for an SMT processor with a virtually-indexed based cache implementation, existing instruction fetching mechanisms can induce unnecessary false cache misses caused by the DLL-based instructions, which were intended to be shared. This problem is more conspicuous when multiple independent threads are executing concurrently in an SMT processor.
This work investigates an often-neglected form of contention between running threads in the I-TLB and I-cache caused by DLLs. To address these shortcomings, we propose a system level technique involving a light-weight modification in the microarchitecture and the OS. By exploiting the nature of the DLLs in our new
architecture, we are able to reinstate physical sharing of the DLLs in an SMT machine. Using Microsoft Windows based applications, our
simulation results show that the optimized instruction fetching mechanism can reduce the number of DLL misses up to 5.5 times and
improve the instruction cache hit rates by up to 62%, resulting in upto 30% DLL IPC improvements and upto 15% overall IPC improvements.
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Distributed JAVA virtual machine with thread migrationZhu, Wenzhang., 朱文章. January 2004 (has links)
published_or_final_version / Computer Science and Information Systems / Doctoral / Doctor of Philosophy
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Distributed object sharing for cluster-based Java virtual machineFang, Weijian., 方維堅. January 2004 (has links)
published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy
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Adaptive transaction scheduling for transactional memory systemsYoo, Richard M. January 2008 (has links)
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Lee, Hsien-Hsin; Committee Member: Blough, Douglas; Committee Member: Yalamanchili, Sudhakar.
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Statically configured heterogeneous SMT processorVellore Suriyakumar, Avinankumar. January 2009 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Computer Science, 2009. / Includes bibliographical references.
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Distributed JAVA virtual machine with thread migration /Zhu, Wenzhang. January 2004 (has links)
Thesis (Ph. D.)--University of Hong Kong, 2005.
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Distributed object sharing for cluster-based Java virtual machine /Fang, Weijian. January 2004 (has links)
Thesis (Ph. D.)--University of Hong Kong, 2005.
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Efficient synchronization for a large-scale multi-core chip architectureZhu, Weirong. January 2007 (has links)
Thesis (D.Eng.)--University of Delaware, 2007. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical and Computer Engineering. Includes bibliographical references.
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The recursive multi-threaded software life-cycleSimon, Scott James 01 January 1997 (has links)
No description available.
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