The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors requires replacement of conventional silicon dioxide layer with higher dielectric constant (K) material for gate dielectric. In order to reduce the gate leakage current, and also to maximize gate capacitance, ‘high K’ gate oxide materials such as Al2O3, ZrO2, HfO2, Ta2O5, TiO2, Er2O3, La2O3, Pr2O3, Gd2O3, Y2O3, CeO2 etc. and some of their silicates such as ZrxSi1–xOy, HfxSi1–xOy, AlxZr1–xO2 etc. are under investigation. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternate gate dielectric are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the materials/process used in CMOS devices and (f) reliability. In this study titanium dioxide (TiO2) is chosen as an alternate to silicon dioxide (SiO2). This thesis work is aimed at the study of the influence of process parameters like deposition rate, substrate temperature and annealing temperature on the electrical properties like maximum capacitance, dielectric constant, fixed charge, interface trapped charge and leakage current. For making this analysis we have used p–type single crystal silicon (<100>) as substrates and employed direct current (DC) reactive magnetron sputtering method with Titanium metal as target and Oxygen as reactive gas. TiO2 thin films have been deposited with an expected thickness of 50 nm with different deposition rates starting from 0.8 nm/minute to 2 nm/minute with different substrate temperatures (ambient temperature to 500ºC). Some of the samples are annealed at 750ºC in oxygen atmosphere for 30 minutes. SENTECH make Spectroscopic Ellipsometer is used for analyzing the optical properties such as thickness, refractive index etc. The thicknesses of all the samples that are extracted from the Ellipsometry are varying from 35 ± 2 nm to 50 ± 5 nm. Agilent make 4284A model L−C−R meter along with KarlSUSS wafer probe station is used for the C − V measurements and Keithley make 6487 model Pico ammeter/Voltage source is used for the I−V measurements. MOS capacitors have been fabricated with Aluminium as top electrode to perform the bi directional Capacitance−Voltage and also Current−Voltage analysis. The X–ray diffraction studies on the samples deposited at 500ºC showed that the films are amorphous. Dielectric constant (K) and effective substrate doping concentration (Na), flat band voltage (VFB), hysteresis, magnitude of fixed charges (Qf) as well as interface states density (Dit') and Equivalent Oxide Thickness (EOT) are obtained from the bi directional C−V analysis. A maximum dielectric constant of 18 is achieved with annealed samples. The best value of fixed charge density we have achieved is 1.2 x1011 per cm2 corresponding to the deposition rate of 2.0 nm/minute and with 500ºC substrate temperature. The ranges of Qf values that we have obtained are varying from 1.2x 1011 − 1.0 x1012 per cm2. It was also found that, the samples deposited at higher substrate temperatures show lower Qf values than the samples deposited at lower temperatures. The same trend is observed in case of interface states density also. The range of Dit' values we have obtained are in the range of 1.0 x 1012 cm–2eV–1 to 9x1012 cm–2eV–1. The best value of Dit' we have obtained is 1.0x1012 cm–2 eV–1 for the sample deposited at 0.8 nm/minute deposition rate and with substrate temperature of 400ºC. From the flat band voltage values of different set of samples, it was found that the flat band voltage is decreasing and in turn trying to approach the analytical value for the films deposited at higher deposition rates. The minimum EOT that we have achieved is 11 nm that corresponds to the film, which is annealed at 750ºC in oxygen atmosphere. From the I−V analysis it was found that the leakage current density is increasing with increase in substrate temperature and the same trend is observed with annealed films also. The minimum leakage current density achieved is 1.72x10–6 A/cm2 at a gate bias of 1V (corresponding field of 0.3 MV/cm). From the time dependent dielectric breakdown analysis it was found that the leakage current is exhibiting a constant value during the entire voltage stress time of 23 minutes. From the I–V characteristics it was found that the leakage current is following the Schottky emission characteristics at lower electric fields (< 1MV/cm) and is following the Fowler–Nordheim tunneling mechanism at higher electric fields. Since our aim is to study the electrical properties of titanium dioxide thin films for the application as high K gate dielectric in microelectronic applications more emphasis is given on the electrical properties. The maximum dielectric constant we have achieved is in the comparable range of the values for this parameter. The leakage current density values obtained are higher than the required for the microelectronic devices, where as the interface state density values and fixed charge density values are in the same range of values that are reported with this particular oxide and more care has to be taken to minimize these parameters. The EOT values we have achieved are also falling into the range of values that it actually takes as it was reported in the literature.