Time-Interleaved Analog to Digital Converters (TI ADC) consist of several individual sub-converters operating at a lower sampling rate, working in parallel, and in a circular loop. Thereby, they are increasing the sampling rate without compromising on the resolution during conversion, at high sampling rates. The latter is the main requirement in the area of radio frequency sampling. However, they suffer from mismatches caused by the different characteristics in each sub-converter and the TI structure. The output of the TI ADC under consideration contains a lot of harmonics and spurious tones due to the non-linearities mismatch between the sub-converters. Therefore, previously extensive frequency planning was performed to avoid the input signal from coinciding with these harmonic bins. More importance has been given to digital calibration in recent years where algorithms are developed and implemented outside ADC in a Digital signal processor (DSP), whereas the compensation is done in real time. In this work, we model the distortions and the harmonics present in the TI ADC output to get a clear understanding of the TI ADC. A post-correction block is developed for the cancellation of the characterized harmonics. The suggested method is tested on the TI ADCs working at radio frequencies, but is valid also for other types of ADCs, such as pipeline ADCs and sigma-delta ADCs.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

<p>Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially.</p><p>Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.</p>

Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially. Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.