Energy consumption is one of the most constrained requirements for the development and implementation of wireless sensor networks. Many design aspects affect energy consumption, ranging from the hardware components, operations of the sensors, the communication protocols, the application algorithms, duty cycles and others. Efficient simulation tool can be used to estimate the contribution to energy consumption of all of these factors, and significantly decrease the efforts and time spent to choose the right solution that fits best to a particular application. In this work we present design space exploration methodology for ultra low power embedded systems and wireless sensor networks. The methodology takes inspiration from Platform Based Design (PBD) paradigm and defines separate abstraction layers for all system aspects that directly contribute power consumption of target applications. To support presented methodology we built a SystemC-based discrete event simulation framework, called “PASES”, that provides power-aware simulation and analysis of wireless sensor networks and sensor nodes. Its modular architecture allows flexible, extensible and rapid modeling of custom HW platforms, SW application models, communication protocols, energy sources, environment dynamics and nodes mobility. Based on the feedback gained from PASES, the optimal and energy-efficient solution for the specific project of interest can be selected. The proposed approach improves state-of-the-art by providing fast and reliable power-aware system-level exploration for a wide range of custom applications

No description available.

The present work aims to provide a contribution to improve the efficiency the design flow of integrated systems, focusing, specifically, on the performance evaluation of its communication structures. The use of Transaction Level Modeling (TLM) is proposed, in order to take advantage of the reduction of design effort and time. Within the performance evaluation approaches, the utilization of traffic generators instead of full system simulations started to be adopted due to its higher time efficiency. Initial works on on-chip traffic generation focused on Poisson processes and classic Markovian models, which are unable to capture Long Range Dependence (LRD). This fact led to the adoption of fractal/self-similar models. Later advancements have shown that the traffic produced in multiprocessed systems can show higher degrees of complexity, what can be attributed to the presence multifractal characteristics. In this work, a methodology to evaluate the on-chip traffic and to the development of a transaction level traffic generator is proposed. The main contributions of this work are a detailed analysis of traffic time series obtained by TLM simulations and the study of the effects of the traffic generator on these simulations, concerning, mainly, the speedup-accuracy trade-off. The proposed analysis follow the multifractal paradigm, allowing system developers to (1) understand the statistical nature of on-chip traffic, (2) to obtain accurate representations of this traffic and (3) to build traffic generators that mimic processing elements realistically. Another contribution of this work is a comparison of the performance, considering the accuracy of the obtained synthetic traffic time series, between monofractal and multifractal models. All of the mentioned contributions were grouped throughout the detailed methodology presented on the present document, for which experiments were carried out. / O presente trabalho visa oferecer uma contribuição para o aumentar a eficiência do fluxo de projeto de sistemas integrados, focando, especificamente, na avaliação do desempenho de suas estruturas de comunicação. É proposta a utilização de simulações com modelos no nível de transações (TLM), com o objetivo de se obter vantagens da redução de esforço e tempo de projeto oferecidos por esta abordagem. Dentro das propostas de análise de desempenho, a utilização de geradores de tráfego ao invés simulações de sistema completo tem sido adotada devido a sua maior eficiência no tempo. Trabalhos iniciais na geração de tráfego intrachip focaram-se em processos de Poisson e em modelos de Markov clássicos, os quais não capturam Dependência de Longa Duração (LRD). Este fato levou a adoção de modelos fractais/auto-similares. Avanços posteriores mostraram que o tráfego produzido pelos elementos de sistemas multiprocessados podem apresentar maior grau de complexidade, que pode ser atribuída à presença de características multifractais. Neste trabalho, é proposta uma metodologia para a avaliação de tráfego intrachip para o desenvolvimento de um gerador de tráfego TLM. As principais contribuições deste trabalho são uma análise detalhada das séries temporais de tráfego obtidas nas simulações TLM e o estudo dos efeitos que o gerador de tráfego exerce sobre estas simulações, se concentrando, principalmente, na relação entre precisão e aceleração da simulação. As análises propostas se baseiam no paradigma multifractal, o qual permite (1) um maior entendimento da natureza estatística do tráfego pelos desenvolvedores de sistemas, (2) a obtenção de uma representação precisa deste tráfego e (3) a construção de geradores de tráfego que substituam elementos processantes de maneira realista. Outra contribuição deste trabalho é a comparação do desempenho, no que concerne a precisão das séries de tráfego sintéticas obtidas, de modelos monofractais e multifractais. Todas as contribuições mencionadas foram agrupadas na metodologia detalhada, apresentada no presente documento, sobre a qual experimentos foram realizados.

Este trabalho visa dar uma contribuição para o aumento de eficiência no fluxo de projeto de sistemas integrados, especificamente na avaliação de desempenho da comunicação entre os seus blocos componentes. É proposto o uso de modelagem e simulação de hardware em alto nível, no nível de transações, denominado TLM, para aproveitar a redução de esforço e tempo que se pode oferecer ao projeto de sistemas integrados, diferentemente de enfoques convencionais em níveis mais baixos de descrição, como o nível de registradores (RTL). É proposta uma forma de análise do tráfego intrachip produzido na comunicação de elementos do sistema, visando-se o uso dos resultados obtidos para descrição de geradores de tráfego. A principal contribuição deste trabalho é a proposta da análise de séries de tráfego obtido durante simulação de plataformas de hardware descritas no nível TLM usando-se métodos estatísticos conhecidos da área de estudo de séries temporais. A análise permite ao projetista ter maior compreensão da natureza estatística do tráfego intrachip, denominada dependência de curta ou longa duração (SRD e LRD), para o posterior ajuste de modelos usados na geração de séries sintéticas que representem tal natureza. Os resultados da análise mostraram que o tráfego obtido por simulação TLM tem natureza similar em relação ao da do tráfego obtido por simulação num nível mais baixo de abstração, do tipo de precisão por ciclos, indicando que o tráfego TLM pode ser usado para a representação do tráfego intrachip. Outra contribuição deste trabalho é a proposta de ajuste de modelos paramétricos autossimilares usando-se a decomposição da série de tráfego original, tendo sido feita uma comparação dos resultados desta com o ajuste convencional feito a modelos sem decomposição. Estas contribuições foram agrupadas dentro de uma metodologia detalhada, apresentada neste documento, para a qual experimentos foram realizados. Os resultados a partir das séries sintéticas autossimilares geradas pelos modelos estimados, apresentaram semelhança nos indicadores de SRD e LRD em relação às séries originais TLM, mostrando ser favorável o uso futuro destas séries sintéticas na implementação de geradores de tráfego. / It is objective of this work to make a contribution to improve the efficiency of the integrated systems design flow, specifically on the evaluation of communication performance between component blocks. The use of high level hardware modeling and simulation, at the transaction level, known as TLM, is proposed, in order to take advantage of the reduction of effort and time for the integrated system design; that in contrast to the traditional approaches, which use lower hardware description level, such as register transfer level (RTL). A methodology to evaluate the intra-chip traffic produced by the communication between system elements is proposed. The main contribution of this work is the analysis of traffic time series obtained by simulation of hardware platforms modeled in TLM, using well-known statistical methods for time series analysis. The analysis allows the system developer to understand the statistical nature of the intra-chip traffic, also known as short and long range dependence (SRD and LRD), for later adjustment and accurate representation of the traffic nature in synthetic series. The analysis results have shown that traffic traces obtained by TLM simulation has similar statistical nature as the traffic traces obtained at lower abstraction level, as cycle accurate type, which indicates that TLM traffic could be used to represent intrachip traffic. Another contribution of this work is a fitting procedure to auto similar parametric models thought the decomposition of the original traffic, and its comparison to the results of the conventional fitting, when applied to models that are not decomposed. These contributions were grouped and included in the detailed methodology presented in this document, being a series of experiments carried out. The results related to self-similar synthetic series, obtained from the fitted models, have shown similarity to the SRD and LRD indicators of the original TLM series, what favors the use of synthetic series future for the implementation of traffic generators.

Cette thèse porte sur la modélisation des systèmes-sur-puce au niveau transactionnel, une approche connue sous le nom de prototypage virtuel. Les prototypes virtuels sont d'un grand intérêt industriel parce qu'ils permettent de démarrer certaines activités (telles que le développement du logiciel embarqué) plus tôt dans le flot de conception. Du fait que cette approche est relativement nouvelle, un grand nombre de problèmes de modélisation sont encore ouverts. En particulier, il est essentiel de comprendre à quel point un modèle donné est proche du système hypothétique qu'il est sensé représenter. C'est un problème difficile car nous n'avons pas les moyens de réaliser une comparaison objective, vu que le système modélisé n'est pas disponible physiquement au moment de la modélisation. Nous avons besoin d'une méthodologie pour traiter ces difficultés, qui s'étendent au-delà de simples exigences objectives et de l'analyse de besoin fonctionnel. Dans ce contexte, l'industrie cherche des directives de modélisation claires, fondées sur l'expérience et l'identification des pratiques actuelles et des problèmes récurrents. Dans cette thèse, nous présentons une étude compréhensive d'un large éventail de considérations techniques impliquées dans le flot de conception du logiciel et du matériel qui constituent un système-sur-puce typique. Nous utilisons ces connaissances pour identifier une source particulière de divergence entre le modèle et le système modélisé. Nous montrons que cette divergence masque certains bogues du logiciel sur le prototype virtuel. Nous mettons en évidence la pratique de modélisation à l'origine de cette situation. Deuxièmement, nous essayons d'identifier des problèmes liés à l'utilisation du langage de modélisation dans les pratiques actuelles. Nous prétendons que, d'une part, ces problèmes sont dûs à la confusion entre les concepts de la modélisation transactionnelle et leur implémentation dans le langage standard de l'industrie ; et d'autre part que ce n'est qu'en menant des comparaisons avec un autre langage que l'on pourrait quantifier leur étendue. Pour ce faire, nous proposons un cadre d'application spécialement conçu pour guider l'étude des concepts fondamentaux de la modélisation transactionnelle. Entre autres, nous introduisons une nouvelle méthode pour la modélisation du temps dans les simulateurs à événements discrets. Cette méthode dévoile la différence entre une action instantanée et une tâche avec durée. Ensuite, elle l'exploite de plusieurs manières : pour enrichir les outils de visualisation de traces ; pour dériver une définition claire de chevauchement de tâches ; pour accélérer la simulation à moindre effort, en parallélisant l'exécution d'actions se déroulant à des temps simulés différents ; et pour révéler des bogues subtiles en tenant compte du fait que les actions à des temps simulés différents ne sont pas forcément synchronisées. / This thesis deals with modeling of Systems-on-a-Chip (SoC) at the Transactional Level (TLM), an approach also known as virtual prototyping. Virtual prototypes are of special industrial interest because they allow some activities (such as embedded software development) to start earlier in the design flow. Because this approach is relatively new, several modeling issues are still open. In particular, there is an increasing need for understanding how close a given model is to the hypothetical system it is intended to represent. This is a difficult problem specially because we lack a way to perform an objective comparison, since the modeling activity is prior to the physical existence of the modeled system. A methodology is required to address these concerns, going beyond classical objective and functional quality requirements. In this context, the industry searches for clear modeling guidelines based on experience and the identification of the current modeling practices and known recurring problems. In this thesis, we present a comprehensive study of a range of technical considerations involved in the design flow of the hardware and software that constitutes a typical SoC. We use this knowledge to identify one particular source of divergence between the model and the modeled system. We show that this divergence causes some software bugs to become hidden in the virtual prototype and we correlate this situation to the corresponding modeling practice. Secondly, we attempt to identify language-dependency issues in the modeling practices. We claim that it is only by confronting with an alternative language that we could measure the extent to which common modeling issues were caused by mixing up conceptual transaction-level modeling with its implementation in the current industry standard language. Therefore, we propose a complete experimentation framework specifically designed to help in the study of fundamental concepts beneath TLM. Amongst other features, this framework introduces a novel approach to modeling time in discrete-event simulators that distinguishes between instantaneous actions and tasks that take time. We show that this notion can be exploited to enrich trace visualization tools; to derive a clear definition of overlapping tasks; to effortlessly achieve an important simulation speedup by enabling parallel execution of actions occurring at different simulation times; and to expose subtle bugs by removing the constraint that actions at different simulation times are necessarily synchronized.

The present work aims to provide a contribution to improve the efficiency the design flow of integrated systems, focusing, specifically, on the performance evaluation of its communication structures. The use of Transaction Level Modeling (TLM) is proposed, in order to take advantage of the reduction of design effort and time. Within the performance evaluation approaches, the utilization of traffic generators instead of full system simulations started to be adopted due to its higher time efficiency. Initial works on on-chip traffic generation focused on Poisson processes and classic Markovian models, which are unable to capture Long Range Dependence (LRD). This fact led to the adoption of fractal/self-similar models. Later advancements have shown that the traffic produced in multiprocessed systems can show higher degrees of complexity, what can be attributed to the presence multifractal characteristics. In this work, a methodology to evaluate the on-chip traffic and to the development of a transaction level traffic generator is proposed. The main contributions of this work are a detailed analysis of traffic time series obtained by TLM simulations and the study of the effects of the traffic generator on these simulations, concerning, mainly, the speedup-accuracy trade-off. The proposed analysis follow the multifractal paradigm, allowing system developers to (1) understand the statistical nature of on-chip traffic, (2) to obtain accurate representations of this traffic and (3) to build traffic generators that mimic processing elements realistically. Another contribution of this work is a comparison of the performance, considering the accuracy of the obtained synthetic traffic time series, between monofractal and multifractal models. All of the mentioned contributions were grouped throughout the detailed methodology presented on the present document, for which experiments were carried out. / O presente trabalho visa oferecer uma contribuição para o aumentar a eficiência do fluxo de projeto de sistemas integrados, focando, especificamente, na avaliação do desempenho de suas estruturas de comunicação. É proposta a utilização de simulações com modelos no nível de transações (TLM), com o objetivo de se obter vantagens da redução de esforço e tempo de projeto oferecidos por esta abordagem. Dentro das propostas de análise de desempenho, a utilização de geradores de tráfego ao invés simulações de sistema completo tem sido adotada devido a sua maior eficiência no tempo. Trabalhos iniciais na geração de tráfego intrachip focaram-se em processos de Poisson e em modelos de Markov clássicos, os quais não capturam Dependência de Longa Duração (LRD). Este fato levou a adoção de modelos fractais/auto-similares. Avanços posteriores mostraram que o tráfego produzido pelos elementos de sistemas multiprocessados podem apresentar maior grau de complexidade, que pode ser atribuída à presença de características multifractais. Neste trabalho, é proposta uma metodologia para a avaliação de tráfego intrachip para o desenvolvimento de um gerador de tráfego TLM. As principais contribuições deste trabalho são uma análise detalhada das séries temporais de tráfego obtidas nas simulações TLM e o estudo dos efeitos que o gerador de tráfego exerce sobre estas simulações, se concentrando, principalmente, na relação entre precisão e aceleração da simulação. As análises propostas se baseiam no paradigma multifractal, o qual permite (1) um maior entendimento da natureza estatística do tráfego pelos desenvolvedores de sistemas, (2) a obtenção de uma representação precisa deste tráfego e (3) a construção de geradores de tráfego que substituam elementos processantes de maneira realista. Outra contribuição deste trabalho é a comparação do desempenho, no que concerne a precisão das séries de tráfego sintéticas obtidas, de modelos monofractais e multifractais. Todas as contribuições mencionadas foram agrupadas na metodologia detalhada, apresentada no presente documento, sobre a qual experimentos foram realizados.

Este trabalho visa dar uma contribuição para o aumento de eficiência no fluxo de projeto de sistemas integrados, especificamente na avaliação de desempenho da comunicação entre os seus blocos componentes. É proposto o uso de modelagem e simulação de hardware em alto nível, no nível de transações, denominado TLM, para aproveitar a redução de esforço e tempo que se pode oferecer ao projeto de sistemas integrados, diferentemente de enfoques convencionais em níveis mais baixos de descrição, como o nível de registradores (RTL). É proposta uma forma de análise do tráfego intrachip produzido na comunicação de elementos do sistema, visando-se o uso dos resultados obtidos para descrição de geradores de tráfego. A principal contribuição deste trabalho é a proposta da análise de séries de tráfego obtido durante simulação de plataformas de hardware descritas no nível TLM usando-se métodos estatísticos conhecidos da área de estudo de séries temporais. A análise permite ao projetista ter maior compreensão da natureza estatística do tráfego intrachip, denominada dependência de curta ou longa duração (SRD e LRD), para o posterior ajuste de modelos usados na geração de séries sintéticas que representem tal natureza. Os resultados da análise mostraram que o tráfego obtido por simulação TLM tem natureza similar em relação ao da do tráfego obtido por simulação num nível mais baixo de abstração, do tipo de precisão por ciclos, indicando que o tráfego TLM pode ser usado para a representação do tráfego intrachip. Outra contribuição deste trabalho é a proposta de ajuste de modelos paramétricos autossimilares usando-se a decomposição da série de tráfego original, tendo sido feita uma comparação dos resultados desta com o ajuste convencional feito a modelos sem decomposição. Estas contribuições foram agrupadas dentro de uma metodologia detalhada, apresentada neste documento, para a qual experimentos foram realizados. Os resultados a partir das séries sintéticas autossimilares geradas pelos modelos estimados, apresentaram semelhança nos indicadores de SRD e LRD em relação às séries originais TLM, mostrando ser favorável o uso futuro destas séries sintéticas na implementação de geradores de tráfego. / It is objective of this work to make a contribution to improve the efficiency of the integrated systems design flow, specifically on the evaluation of communication performance between component blocks. The use of high level hardware modeling and simulation, at the transaction level, known as TLM, is proposed, in order to take advantage of the reduction of effort and time for the integrated system design; that in contrast to the traditional approaches, which use lower hardware description level, such as register transfer level (RTL). A methodology to evaluate the intra-chip traffic produced by the communication between system elements is proposed. The main contribution of this work is the analysis of traffic time series obtained by simulation of hardware platforms modeled in TLM, using well-known statistical methods for time series analysis. The analysis allows the system developer to understand the statistical nature of the intra-chip traffic, also known as short and long range dependence (SRD and LRD), for later adjustment and accurate representation of the traffic nature in synthetic series. The analysis results have shown that traffic traces obtained by TLM simulation has similar statistical nature as the traffic traces obtained at lower abstraction level, as cycle accurate type, which indicates that TLM traffic could be used to represent intrachip traffic. Another contribution of this work is a fitting procedure to auto similar parametric models thought the decomposition of the original traffic, and its comparison to the results of the conventional fitting, when applied to models that are not decomposed. These contributions were grouped and included in the detailed methodology presented in this document, being a series of experiments carried out. The results related to self-similar synthetic series, obtained from the fitted models, have shown similarity to the SRD and LRD indicators of the original TLM series, what favors the use of synthetic series future for the implementation of traffic generators.

Les systèmes Matériels/Logiciels deviennent indispensables dans tous les aspects de la vie quotidienne. La présence croissante de ces systèmes dans les différents produits et services incite à trouver des méthodes pour les développer efficacement. Mais une conception efficace de ces systèmes est limitée par plusieurs facteurs, certains d'entre eux sont: la complexité croissante des applications, une augmentation de la densité d'intégration, la nature hétérogène des produits et services, la diminution de temps d’accès au marché. Une modélisation transactionnelle (TLM) est considérée comme un paradigme prometteur permettant de gérer la complexité de conception et fournissant des moyens d’exploration et de validation d'alternatives de conception à des niveaux d’abstraction élevés. Cette recherche propose une méthodologie d’expression de temps dans TLM basée sur une analyse de contraintes temporelles. Nous proposons d'utiliser une combinaison de deux paradigmes de développement pour accélérer la conception: le TLM d'une part et une méthodologie d’expression de temps entre différentes transactions d’autre part. Cette synergie nous permet de combiner dans un seul environnement des méthodes de simulation performantes et des méthodes analytiques formelles. Nous avons proposé un nouvel algorithme de vérification temporelle basé sur la procédure de linéarisation des contraintes de type min/max et une technique d'optimisation afin d'améliorer l'efficacité de l'algorithme. Nous avons complété la description mathématique de tous les types de contraintes présentées dans la littérature. Nous avons développé des méthodes d'exploration et raffinement de système de communication qui nous a permis d'utiliser les algorithmes de vérification temporelle à différents niveaux TLM. Comme il existe plusieurs définitions du TLM, dans le cadre de notre recherche, nous avons défini une méthodologie de spécification et simulation pour des systèmes Matériel/Logiciel basée sur le paradigme de TLM. Dans cette méthodologie plusieurs concepts de modélisation peuvent être considérés séparément. Basée sur l'utilisation des technologies modernes de génie logiciel telles que XML, XSLT, XSD, la programmation orientée objet et plusieurs autres fournies par l’environnement .Net, la méthodologie proposée présente une approche qui rend possible une réutilisation des modèles intermédiaires afin de faire face à la contrainte de temps d’accès au marché. Elle fournit une approche générale dans la modélisation du système qui sépare les différents aspects de conception tels que des modèles de calculs utilisés pour décrire le système à des niveaux d’abstraction multiples. En conséquence, dans le modèle du système nous pouvons clairement identifier la fonctionnalité du système sans les détails reliés aux plateformes de développement et ceci mènera à améliorer la "portabilité" du modèle d'application. / Hardware/Software (Hw/Sw) systems are likely to become essential in all aspects of everyday life. The increasing penetration of Hw/Sw systems in products and services creates a necessity of their efficient development. However, the productive design of these systems is limited by several factors, some of them being the increasing complexity of applications, the increasing degree of integration, the heterogeneous nature of products and services as well as the shrinking of the time-to-market delay. Transaction Level Modeling (TLM) paradigm is considered as one of the most promising simulation paradigms to break down the design complexity by allowing the exploration and validation of design alternatives at high levels of abstraction. This research proposes a timing expression methodology in TLM based on temporal constraints analysis. We propose to use a combination of two paradigms to accelerate the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand. Using a timing specification model and underlining timing constraints verification algorithms can decrease the time needed for verification by simulation. Combining in one framework the simulation and analytical design exploration methods can improve the analytical power of design verification and validation. We have proposed a new timing verification algorithm based on the linearization procedure and an optimization technique to improve its efficiency. We have completed the mathematical representation of all constraint types discussed in the literature creating in this way a unified timing specification methodology that can be used in the expression of a wider class of applications than previously presented ones. We have developed the methods for communication structure exploration and refinement that permitted us to apply the timing verification algorithms in system exploration at different TLM levels. As there are many definitions of TLM and many development environments proposing TLM in their design cycle with several pro and contra, in the context of our research we define a hardware/software (Hw/Sw) specification and simulation methodology which supports TLM in such a way that several modeling concepts can be seen separately. Relying on the use of modern software engineering technologies such as XML, XSLT, XSD, object oriented programming and others supported by the .Net Framework, an approach that makes an intermediate design model reuse possible in order to cope with time-to-market constraint is presented. The proposed TLM design methodology provides a general approach in system modeling that separates various application modeling aspects from system specification: computational models, used in application modeling, supported by the language used for the functional specification and provided by simulator. As a result, in the system model we can clearly identify system functionality without details related to the development platform thereby leading to a better “portability” of the application model.

Les systèmes Matériels/Logiciels deviennent indispensables dans tous les aspects de la vie quotidienne. La présence croissante de ces systèmes dans les différents produits et services incite à trouver des méthodes pour les développer efficacement. Mais une conception efficace de ces systèmes est limitée par plusieurs facteurs, certains d'entre eux sont: la complexité croissante des applications, une augmentation de la densité d'intégration, la nature hétérogène des produits et services, la diminution de temps d’accès au marché. Une modélisation transactionnelle (TLM) est considérée comme un paradigme prometteur permettant de gérer la complexité de conception et fournissant des moyens d’exploration et de validation d'alternatives de conception à des niveaux d’abstraction élevés. Cette recherche propose une méthodologie d’expression de temps dans TLM basée sur une analyse de contraintes temporelles. Nous proposons d'utiliser une combinaison de deux paradigmes de développement pour accélérer la conception: le TLM d'une part et une méthodologie d’expression de temps entre différentes transactions d’autre part. Cette synergie nous permet de combiner dans un seul environnement des méthodes de simulation performantes et des méthodes analytiques formelles. Nous avons proposé un nouvel algorithme de vérification temporelle basé sur la procédure de linéarisation des contraintes de type min/max et une technique d'optimisation afin d'améliorer l'efficacité de l'algorithme. Nous avons complété la description mathématique de tous les types de contraintes présentées dans la littérature. Nous avons développé des méthodes d'exploration et raffinement de système de communication qui nous a permis d'utiliser les algorithmes de vérification temporelle à différents niveaux TLM. Comme il existe plusieurs définitions du TLM, dans le cadre de notre recherche, nous avons défini une méthodologie de spécification et simulation pour des systèmes Matériel/Logiciel basée sur le paradigme de TLM. Dans cette méthodologie plusieurs concepts de modélisation peuvent être considérés séparément. Basée sur l'utilisation des technologies modernes de génie logiciel telles que XML, XSLT, XSD, la programmation orientée objet et plusieurs autres fournies par l’environnement .Net, la méthodologie proposée présente une approche qui rend possible une réutilisation des modèles intermédiaires afin de faire face à la contrainte de temps d’accès au marché. Elle fournit une approche générale dans la modélisation du système qui sépare les différents aspects de conception tels que des modèles de calculs utilisés pour décrire le système à des niveaux d’abstraction multiples. En conséquence, dans le modèle du système nous pouvons clairement identifier la fonctionnalité du système sans les détails reliés aux plateformes de développement et ceci mènera à améliorer la "portabilité" du modèle d'application. / Hardware/Software (Hw/Sw) systems are likely to become essential in all aspects of everyday life. The increasing penetration of Hw/Sw systems in products and services creates a necessity of their efficient development. However, the productive design of these systems is limited by several factors, some of them being the increasing complexity of applications, the increasing degree of integration, the heterogeneous nature of products and services as well as the shrinking of the time-to-market delay. Transaction Level Modeling (TLM) paradigm is considered as one of the most promising simulation paradigms to break down the design complexity by allowing the exploration and validation of design alternatives at high levels of abstraction. This research proposes a timing expression methodology in TLM based on temporal constraints analysis. We propose to use a combination of two paradigms to accelerate the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand. Using a timing specification model and underlining timing constraints verification algorithms can decrease the time needed for verification by simulation. Combining in one framework the simulation and analytical design exploration methods can improve the analytical power of design verification and validation. We have proposed a new timing verification algorithm based on the linearization procedure and an optimization technique to improve its efficiency. We have completed the mathematical representation of all constraint types discussed in the literature creating in this way a unified timing specification methodology that can be used in the expression of a wider class of applications than previously presented ones. We have developed the methods for communication structure exploration and refinement that permitted us to apply the timing verification algorithms in system exploration at different TLM levels. As there are many definitions of TLM and many development environments proposing TLM in their design cycle with several pro and contra, in the context of our research we define a hardware/software (Hw/Sw) specification and simulation methodology which supports TLM in such a way that several modeling concepts can be seen separately. Relying on the use of modern software engineering technologies such as XML, XSLT, XSD, object oriented programming and others supported by the .Net Framework, an approach that makes an intermediate design model reuse possible in order to cope with time-to-market constraint is presented. The proposed TLM design methodology provides a general approach in system modeling that separates various application modeling aspects from system specification: computational models, used in application modeling, supported by the language used for the functional specification and provided by simulator. As a result, in the system model we can clearly identify system functionality without details related to the development platform thereby leading to a better “portability” of the application model.

Les travaux présentés dans cette thèse portent sur la modélisation, la spécification et la vérification des modèlesdes Systèmes sur Puce (SoCs) au niveau d’abstraction transactionnel et à un niveau d’abstraction plus élevé.Les SoCs sont hétérogènes: ils comprennent des composants matériels et des processeurs pour réaliser le logicielincorporé, qui est en lien direct avec du matériel. La modélisation transactionnelle (TLM) basée sur SystemCa été très fructueuse à fournir des modèles exécutables des SoCs à un haut niveau d’abstraction, aussi appelésprototypes virtuels (VPs). Ces modèles peuvent être utilisés plus tôt dans le cycle de développement des logiciels,et la validation des matériels réels. La vérification basée sur assertions (ABV) permet de vérifier les propriétés tôtdans le cycle de conception de façon à trouver les défauts et faire gagner du temps et de l’effort nécessaires pourla correction de ces défauts. Les modèles TL peuvent être sur-contraints, c’est-à-dire qu’ils ne presentent pastous les comportements du matériel. Ainsi, ceci ne permet pas la détection de tous les défauts de la conception.Nos contributions consistent en deux parties orthogonales et complémentaires: D’une part, nous identifions lessources des sur-contraintes dans les modèles TLM, qui apparaissent à cause de l’ordre d’interaction entre lescomposants. Nous proposons une notion d’ordre mou qui permet la suppression de ces sur-contraintes. D’autrepart, nous présentons un mécanisme généralisé de stubbing qui permet la simulation précoce avec des prototypesvirtuels SystemC/TLM.Nous offrons un jeu de patrons pour capturer les propriétés d’ordre mou et définissons une transformationdirecte de ces patrons en moniteurs SystemC. Notre mécanisme généralisé du stubbing permet la simulationprécoce avec les prototypes virtuels SystemC/TLM, dans lesquels certains composants ne sont pas entièrementdéterminés sur les valeurs des données échangées, l’ordre d’interaction et/ou le timing. Ces composants nepossèdent qu’une spécification abstraite, sous forme de contraintes entre les entrées et les sorties. Nous montronsque les problèmes essentielles de la synchronisation entre les composants peuvent être capturés à l’aide de notresimulation avec les stubs. Le mécanisme est générique; nous mettons l’accent uniquement sur les concepts-clés,les principes et les règles qui rendent le mécanisme de stubbing implémentable et applicable aux études de casindustriels. N’importe quel language de spécification satisfaisant nos exigences (par ex. le langage des ordresmou) peut être utilisé pour spécifier les composants, c’est-à-dire il peut être branché au framework de stubbing.Nous fournissons une preuve de concept pour démontrer l’intérêt d’utiliser la simulation avec stubs pour ladétection anticipée et la localisation des défauts de synchronisation du modèle. / The work presented in this thesis deals with modeling, specification and testing of models of Systems-on-a-Chip (SoCs) at the transaction abstraction level and higher. SoCs are heterogeneous: they comprise bothhardware components and processors to execute embedded software, which closely interacts with hardware.SystemC-based Transaction Level Modeling (TLM) has been very successful in providing high-level executablecomponent-based models for SoCs, also called virtual prototypes (VPs). These models can be used early in thedesign flow for the development of the software and the validation of the actual hardware. For SystemC/TLMvirtual prototypes, Assertion-Based Verification (ABV) allows property checking early in the design cycle,helping to find bugs early in the model and to save time and effort that are needed for their fixing. TL modelscan be over-constrained, which means that they do not represent all the behaviors of the hardware, and thus,do not allow detection of some malfunctions of the prototype. Our contributions consist of two orthogonal andcomplementary parts: On the one hand, we identify sources of over-constraints in TL models appearing due tothe order of interactions between components, and propose a notion of loose-ordering which allows to removethese over-constraints. On the other hand, we propose a generalized stubbing mechanism which allows the veryearly simulation with SystemC/TLM virtual prototypes.We propose a set of patterns to capture loose-ordering properties, and define a direct translation of thesepatterns into SystemC monitors. Our generalized stubbing mechanism enables the early simulation with Sys-temC/TLM virtual prototypes, in which some components are not entirely determined on the values of theexchanged data, the order of the interactions and/or the timing. Those components have very abstract speci-fications only, in the form of constraints between inputs and outputs. We show that essential synchronizationproblems between components can be captured using our simulation with stubs. The mechanism is generic;we focus only on key concepts, principles and rules which make the stubbing mechanism implementable andapplicable for real, industrial case studies. Any specification language satisfying our requirements (e.g., loose-orderings) can be used to specify the components, i.e., it can be plugged in the stubbing framework. We providea proof of concept to demonstrate the interest of using the simulation with stubs for very early detection andlocalization of synchronization bugs of the design.