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Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / A technique for measuring and characterizing transistor noise is presented. The primary goal of the measurements is to locate the 1/f noise corner for select transistors in Silicon-on-Sapphire processes. Additionally, the magnitude of the background channel noise of each transistor is measured. With this data, integrated circuit (IC) engineers will have a qualitative and quantitative resource for selecting transistors in designs with low noise requirements. During tests, transistor noise behavioral change is investigated over varying channel lengths, device type (N-type and P-type), threshold voltage, and bias voltage levels. Noise improvements for increased channel lengths from minimal, 1.0μm, and 4.0μm are measured. Transistors with medium and high threshold voltages are tested for comparison of their noise performance. The bias voltages are chosen to represent typical design values used in practice, with approximately 400 mV overdrive and a drain-to-source voltage range of 0.5 to 3.0V. The transistors subjected to tests are custom designed in Peregrine’s 0.5μm (FC) and 0.25μm (GC) Silicon-on-Sapphire (SOS) processes. In order to allow channel current noise to dominate over other circuit noise, the transistors have extraordinarily large aspect ratios (~2500 - 5000). The transistor noise produced is amplified and measured over a frequency range of 1kHz - 100MHz. This range allows the measurement of each device’s low and high frequency noise spectrum and resulting noise corner.

The ever increasing diversity in communication systems has created a demand for constant improvements in receiver components. This thesis describes the design and characterisation of front-end receiver components for various challenging applications, including characterisation of low noise foundry processes, LNA design and multi-band antenna design. It also includes a new theoretical analysis of noise coupling in low noise phased array receivers.In LNA design much depends on the choice of the optimum active devices. A comprehensive survey of the performance of low noise transistors is therefore extremely beneficial. To this end a comparison of the DC, small-signal and noise behaviours of 10 state-of-the-art GaAs and InP based pHEMT and mHEMT low noise processes has been carried out. Their suitability in LNA designs has been determined, with emphasis on the SKA project. This work is part of the first known detailed investigation of this kind. Results indicate the superiority of mature GaAs-based pHEMT processes, and highlight problems associated with the studied mHEMT processes. Two of the more promising processes have then been used to design C-band and UHF-band MMIC LNAs. A new theoretical analysis of coupled noise between antenna elements of a low noise phased array receiver has been carried out. Results of the noise wave analysis, based on fundamental principles of noisy networks, suggest that the coupled noise contribution to system noise temperatures should be smaller than had previously been suggested for systems like the SKA. The principles are applicable to any phased array receiver. Finally, a multi-band antenna has been designed and fabricated for a severe operating environment, covering the three extremely crowded frequency bands, the 2.1 GHz UMTS, the 2.4 GHz ISM and the 5.8 GHz ISM bands. Measurements have demonstrated excellent performance, exceeding that of equivalent commercial antennas aimed at similar applications.