Thesis (Ph.D.)--Virginia Commonwealth University, 2009. / Prepared for: Dept. of Electrical Engineering. Title from resource description page. Includes bibliographical references.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1980. / Typescript. Vita. Description based on print version record. Includes bibliographical references (leaves 85-89).

Thesis (M.S.)--University of Wisconsin--Madison, 1968. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

The method of fabrication, the theory and the properties of evaporated silicon thin-film transistors are discussed. The device consists of a p-type silicon film (0.5 to 2µ thick) on a sapphire substrate, with aluminum source-drain electrodes evaporated onto the silicon and followed by a silicon oxide, SiOx , insulating layer and an aluminum gate. The device operates by field-effect conductivity modulation of an n-type inversion layer at the surface of the p-type film. The silicon films were evaporated by electron beam heating in a typical vacuum of 7 x 10⁻⁷ mm Hg at a rate of 200-600 Å/min. The films exhibited single crystal diffraction patterns when deposited at a substrate temperature in the range 1050°C to 1100°C. They were found to be high resistivity ( > 400 Ω -cm) p-type and the hole mobility was of the order of 20-30 cm² /volt-sec. The minority carrier lifetime, was 1-2 µsec and the optical absorption edge of the films was found to be broader than the absorption edge of single crystal silicon at all substrate temperatures. The low carrier mobility and minority carrier lifetime as well as the broadening of the optical absorption edge are attributed to the presence of a large number of crystallographic defects in the films. The effective surface state density at the Si/ evaporated SiOx interface was estimated by the MOS technique and was found to be of the same order of magnitude (3 - 4 x 10¹¹ cm⁻² ) as that at the Si/thermally grown SiO₂ interface. The silicon surface potential in the MOS structure was found to be particularly susceptible to water vapour and contamination by sodium. The silicon thin-film transistors fabricated have typical effective mobilities of 5-10 cm² /volt-sec with transconductances as high as 100 µmho and gain-bandwidth products up to 1 MHz. Surface trapping was found to affect the behavior of the devices at low gate voltages. The characterization of the traps by a method which involves measurements of the source-drain conductance, its temperature dependence and its transient response is discussed. The effect of surface scattering on the mobility at high gate voltages is also considered. The device characteristics were stable in vacuum but drifted when exposed to the atmosphere. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

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Le marché des amplificateurs de puissance pour les combinés téléphoniques portables est actuellement dominé par les semi-conducteurs III-V, les transistors HBT et PHEMT GaAs étant utilisés dans les amplificateurs de puissances et les commutateurs d’antennes respectivement. Cette situation est cependant en train d’évoluer puisque des technologies silicium sur isolant (SOI, Silicon-On-Insulator) intégrant à la fois l’amplificateur de puissance (avec des transistors LDMOS) et les commutateurs d’antennes (avec des transistors CMOS ou des MEMS) sont en cours de qualification. Toutefois, les performances de ces transistors à grille polysilicium, intégrés aux technologies CMOS, limitent leur utilisation à des fréquences de travail inférieures à 2 GHz. L’objectif des travaux de thèse présentés dans ce manuscrit est d’étendre le domaine d’applications des transistors LDMOS aux réseaux de communication sans fil fonctionnant dans une gamme de fréquences de 3 à 5 GHz. Dans cette perspective, une première étude sur différents substrats SOI et massifs a permis de conclure que les substrats de type SOI mince pénalisent les performances des composants LDMOS, notamment à cause de l’effet d’auto-échauffement qui est plus important. Une seconde étude axée sur la structure même du composant indique qu’une modification du contact de grille permet d’augmenter de façon significative les performances en petit signal mais l’amélioration des performances grand signal est plus modérée. Enfin, une étude plus amont qui vise à remplacer le polysilicium des grilles par un métal a montré que la co-intégration de transistors CMOS classiques avec des transistors LDMOS à grille métallique est possible. / The power amplifier market for mobile phone handsets is currently dominated by III-V semiconductors, the PHEMT and HBT GaAs transistors being used for the power amplifiers and the antenna switches respectively. However, this situation is evolving with the release of Silicon-On-Insulator (SOI) technologies which allow the integration of both the power amplifier (with LDMOS transistors) and the antennae switches (with CMOS transistors or MEMS). The performances of the polysilicon gate LDMOS transistors, integrated in CMOS technologies, limits however the operatinq frequency of the power amplifiers to below 2 GHz. The aim of the thesis work presented in this manuscript is to extend the applications of LDMOS transistors to the wireless communication networks operating in the 3 to 5 GHz frequency range. In this perspective, an initial study on different SOI and bulk substrates concluded that thin SOI substrates penalize the performances of RF LDMOS transistors mainly because of the increase of the self-heating effect. A second study focused on the transistor layout shows that a change in the gate contact scheme can significantly increase the small signal performances but the improvement of the large signal performances is more moderate. Finally, a more advanced study which aims to replace polysilicon gates by metal exhibited that the co-integration of conventional CMOS transistors with metal-gate LDMOS transistors is possible.