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Complementary delta-doped AlGaAs/GaAs Heterojunction Field Effect Transistor (CHFET) devices and circuits were fabricated using MBE and a 2�� non-planar gate recess process. Several schemes were used in an attempt to improve the performance of the p-channel HFETs. These included delta-doping, carbon-doping and dipole-doping. Circuits and individual n- and p- channel devices were fabricated on a stacked delta-doped complementary structure. The circuits failed to perform due to complications with adjusting the threshold voltage. However, Individual devices were successfully characterized, p-channel devices with extrinsic transconductances up to 14 mS/mm, n-channel devices with extrinsic transconductances up to 120 mS/mm and a unity power gain bandwidth of 5.5 GHz. / Graduation date: 1995

Graduation date: 1994

The thesis represents a major contribution to the understanding of the design and fabrication of high-voltage planar silicon bipolar transistors, and reports on the original research carried out and the special methods evolved leading to the successful design, development and industrialization of two highly specialized transistors. The development of these transistors, destined for high-reliability applications in subscriber telephone systems, was funded by the South African Department of Posts and Telecommunications. The first device developed was a discrete transistor meeting the requirements of a singularly difficult specification that included the following. An accurately controlled upper limit to quasi-saturation operation, so that above a collector-emitter voltage of 4 V at 60 mA, the device characteristics should be extremely linear. An extremely small range of acceptable gains, with lower and upper limits of 80 and 180 respectively. Both accurately reproducible and high breakdown-voltages exceeding 200 V. The ability to withstand 100 W pulses of 10ps duration at a case temperature of 95 °c and a collector-emitter voltage of 130 V. The second device represents a design and development breakthrough resulting in a unique high-voltage integrated Darlington transistor incorporating the following design features. The standard discrete high-voltage transistors used initially in the Darlington application were found to fail frequently due to an external breakdown mechanism under lightning surge conditions, which are common in South Africa. To overcome this weakness, the integrated Darlington incorporates a special clamping circuit to absorb the surge energy non-destructively within the bulk of the device and thereby prevent external breakdown. To act as an electrostatic shielding system a new 'inverted metallization structure' was developed and incorporated in the Darlington transistor design. With this structure it was possible to realize transistors with a combination of extremely high gains, approaching 105 , and very low collector-emitter leakage currents, often lower than 1 nA at an applied 240 V, and no device with comparable properties has been reported on elsewhere. During the development of the integrated Darlington it was recognized that there was a necessity for a simple yet accurate method of predicting quasi-saturation operation. This consideration led to the development of a totally new, user-orientated, graphical model for predicting the gain of a transistor when operating in the quasi-saturation mode a model involving the use of entirely new yet easily measured parameters. The model was successfully applied to the verification of the Darlington design and the optimization of processing parameters for the device. Although undertaken in a research environment, the projects were handled under pressures normally associated with industrial conditions. Time schedules were constrained, and this influenced design strategy. As a consequence, however, the need arose to develop fast and efficient design aids since much of the theoretical design was implemented for production without recourse to long-term experimental verification in the laboratory. Whilst the author viewed this approach as less than ideal, the successful production of almost two million of these highly specialized devices, including both types, has lent authority to the design techniques developed. In spite of the industry-like pressures imposed during the course of the work, many aspects of the development programmes were further investigated and refined by research that would have been omitted had the author accepted the realization of a working device as the only goal. This research has not only contributed to the production of devices of exceptionally high quality, but has also produced a wealth of new information valuable to future designers. These aids include a new and highly accurate correction for the parasitic collector resistance of a transistor; design data for the specification of epitaxial layers for transistors with collector-emitter breakdown voltages ranging between 5 V and 800 V; information on Gate Associated Transistor (GAT) structures; and the entirely new graphical method, mentioned above, for modelling saturation effects in bipolar transistors. Process development was successfully carried out within the strict confines of compatibility with available equipment, and the pre-requisite that the existing production of low-voltage bipolar integrated circuits should in no way be compromised. Successful transfer of the technology, followed by industrialization, has demonstrated the effectiveness of a method developed by the author for the rapid communication and dissemination of appropriate information in a system without precedents for such procedures. Listed below are other examples showing that useful information was gathered and new techniques developed. Emitter-region defects associated with the metallization process were identified. Test data were used to monitor project performance and in the development of data management techniques. Interaction with the author resulted in the establishment of the first Quality Assurance and Audit function for microelectronics activities by the Department of Posts and Telecommunications in the Republic of South Africa. The group formed had the authority to handle the certification of semiconductor capabilities and the qualification for service of semiconductor components. An entirely new continuous failure analysis programme was introduced covering both the products manufactured and similar types from other sources: a programme that has brought to light the major failure mechanisms in the high-voltage transistors. On the basis of the knowledge gained during the research and development programmes it has been possible to make recommendations, substantiated by preliminary investigations for further original research work on a new type of negative-resistance high-voltage device. This would initially be destined for use in subscriber telephones to improve their immunity to surges, and it would form the basis of the development of a totally new type of interface circuit with in-built protection against surges, for application at the subscriber line interface in electronic exchanges. / Thesis (Ph.D.) - University of Natal, Durban, 1984.

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain. / text

The focus of this thesis involves development of highly transparent, n-channel, accumulation- mode thin-film transistors employing a zinc tin oxide (ZTO) channel layer. ZTO-based transparent thin-film transistors (TTFTs) show improved device performance compared to ZnO-based TTFTs. An estimated peak effective mobility for these devices as high as ~100 cm² V⁻¹sec⁻¹ has been observed, although effective mobilities in the range of 20-50 cm²V⁻¹sec⁻¹ are more common. This performance inconsistency may be due, in part, to the large device dimensions employed in developmental test structures and/or to shadow mask misalignment. Typical drain current on-to-off ratios are > 10⁶. Variation in the post-deposition annealing cycle is found to be an effective means to control the threshold voltage and to improve device performance. Optical characterization of these devices indicates ~84% transparency in the visible spectrum as viewed through the source/drain. Another aspect of this thesis research involves the utilization and extension of quantitative polycrystalline TFT device models with the intention of guiding the design and optimization of future TFTs. In particular, subthreshold conduction is assessed in order to estimate the bulk (and/or grain boundary) and interface trap densities. This leads to a consideration of threshold voltage and channel mobility extraction, as well as establishment of the turn-on voltage, V[subscript turn-on] Finally, a third aspect of this thesis research involves a new radio-frequency (RF) magnetron sputtering system, custom-designed and constructed at OSU by Chris Tasker. Contributions to the development of this tool include assisting in the design and implementation of the computer-controlled interlocks utilized for operation of the tool. The experimental flexibility of this new tool is discussed with respect to its applicability in the design and fabrication of future TTFTS. / Graduation date: 2004

Graduation date: 2006 / A discrete trap model is developed and employed for elucidation of thin-film transistor (TFT) device physics trends. An attractive feature of this model is that only two model parameters are required, the trap energy depth, E[subscript T], and the trap density, N[subscript T]. The most relevant trends occur when E[subscript T] is above the Fermi level. For this case drain current – drain voltage simulations indicate that the drain current decreases with an increase in N[subscript T] and E[subscript T]. The threshold voltage, V[subscript T], extracted from drain current – gate voltage (I[subscript D] – V[[subscript GS]) simulations, is found to be composed of two parts, V[subscript TRAP], the voltage required to fill all the traps and V[subscript ELECTRON], the voltage associated with electrons populating the conduction band. V[subscript T] moves toward a more positive voltage as N[subscript T] and E[subscript T] increase. The inverse subthreshold voltage swing, S, extracted from a log(I[subscript D]) – V[subscript GS] curve, increases as N[subscript T] and E[subscript T] increase. Finally, incremental mobility and average mobility versus gate voltage simulations indicate that the channel mobility decreases with increasing N[subscript T] and E[subscript T].

Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be a potential vehicle for realizing high-speed circuits because of its high electron mobility and low parasitic capacitance. One major drawback of GaAs technology has been the lack of complementary technology in contrast to silicon where CMOS technology has greatly facilitated the development of analog ICs. This thesis investigates the suitability of complementary GaAs Heterojunction FET integrated circuit technology for the realization of high sample-rate switched-capacitor circuits. In order to yield an accurate device model for the design work, model parameters of both n and p GaAs Heterojunction FET devices are extracted from measurement results. Based on the extraction results, a set of analog building blocks are presented. These circuits include a high bandwidth operational amplifier and a fast settling switch which are essential for high sample-rate circuits. A second order switched-capacitor low pass filter sampling at a clock rate of 100MHz is designed using the above building blocks. The designs studied predict better high frequency performance for C-HFETs compared to Si CMOS technology. / Graduation date: 1994

The object of this thesis is to explore the low-frequency noise (LFN) in silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and lateral bipolar junction transistors (BJTs). The LFN of SiGe HBTs and lateral BJTs not only determines the lowest detectable signal limit but also induces phase noise in high-frequency applications. Characterizing the LFN behavior and understanding the physical noise mechanism, therefore, are very important to improve the device and circuit performance. The dissertation achieves the object by investigating the LFN of SiGe HBTs and lateral BJTs with different structures for performance optimization and radiation tolerance, as well as by building models that explain the physical mechanism of LFN in these advance bipolar technologies. The scope of this research is separated into two main parts: the LFN of SiGe HBTs; and the LFN of lateral BJTs. The research in the LFN of SiGe HBTs includes investigating the effects of interfacial oxide (IFO), temperature, geometrical dimensions, and proton radiation. It also includes utilizing physical models to probe noise mechanisms. The research in the LFN of lateral BJTs includes exploring the effects of doping and geometrical dimensions. The research work is envisioned to enhance the understanding of LFN in SiGe HBTs and lateral BJTs.