Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits. / Master of Science

Aplicações móveis que não podem ser recarregadas durante operação, como sensores biomédicos e aplicações da Internet das Coisas, dependem da extração de energia do próprio meio onde se encontram. Tensões de alimentação típicas são normalmente maiores que as disponiveis por métodos de extração de energia do meio e requerem uma conversão de nivel DC que invariavelmente resulta em perdas proporcionais ao fator de conversão. Consequentemente, aplicações projetadas para tensões de alimentação mais próximas da tensão nominal da fonte melhora a eficiência energética. Entretanto, topologias de circuitos elétricos para tensões típicas de alimentação sao impróprias para tensões extremamente baixas. Neste trabalho foram propostas topologias de amplificadores de saída unipolar e diferencial para tensões de alimentaçãoo na casa de centenas de milivolts. As técnicas propostas se baseiam no uso de pares pseudodiferenciais com terminais de corpo polarizados diretamente para vários propósitos, incluindo rejeição de modo comum e polarização de modo comum de saída e corrente DC. Adicionalmente, um oscilador baseado na mesmas técnicas de polarização foi proposto e projetado para duas classes de aplicações: um oscilador de referência intrinsicamente estável e um oscilador controlado por tensão para conversão analógica-digital com melhor linearidade. / Nomadic applications which cannot be recharged while at operation, such as biomedical sensors and Internet of Things applications, rely on energy harvesting from the environment. Typical supply voltages are usually higher than those achieved by energy harvesting methods and requires DC-DC conversion levels, which invariably results in energy loss proportionally to the step of voltage conversion. Consequently, designing at supply voltages closer to the nominal voltage of the energy source improves power efficiency. However, extremely low supply voltages bring design challenges, as circuit topologies for typical voltages employ techniques not suitable for extremely low supply voltages. In this work, single ended and fully differential amplifier topologies for voltage supplies in the range of few hundreds mV were proposed. The proposed approaches use the pseudo differential pairs with the transistor bulk terminals with forward biasing voltages for several purposes, including common mode rejection, output common mode voltage and DC current biasing. Additionally, a ring oscillator based in the same biasing techniques was proposed and designed for two main classes of applications: an intrinsically stable reference oscillator and a voltage controlled oscillator for analog-digital conversion with linearity improvements.

Aplicações móveis que não podem ser recarregadas durante operação, como sensores biomédicos e aplicações da Internet das Coisas, dependem da extração de energia do próprio meio onde se encontram. Tensões de alimentação típicas são normalmente maiores que as disponiveis por métodos de extração de energia do meio e requerem uma conversão de nivel DC que invariavelmente resulta em perdas proporcionais ao fator de conversão. Consequentemente, aplicações projetadas para tensões de alimentação mais próximas da tensão nominal da fonte melhora a eficiência energética. Entretanto, topologias de circuitos elétricos para tensões típicas de alimentação sao impróprias para tensões extremamente baixas. Neste trabalho foram propostas topologias de amplificadores de saída unipolar e diferencial para tensões de alimentaçãoo na casa de centenas de milivolts. As técnicas propostas se baseiam no uso de pares pseudodiferenciais com terminais de corpo polarizados diretamente para vários propósitos, incluindo rejeição de modo comum e polarização de modo comum de saída e corrente DC. Adicionalmente, um oscilador baseado na mesmas técnicas de polarização foi proposto e projetado para duas classes de aplicações: um oscilador de referência intrinsicamente estável e um oscilador controlado por tensão para conversão analógica-digital com melhor linearidade. / Nomadic applications which cannot be recharged while at operation, such as biomedical sensors and Internet of Things applications, rely on energy harvesting from the environment. Typical supply voltages are usually higher than those achieved by energy harvesting methods and requires DC-DC conversion levels, which invariably results in energy loss proportionally to the step of voltage conversion. Consequently, designing at supply voltages closer to the nominal voltage of the energy source improves power efficiency. However, extremely low supply voltages bring design challenges, as circuit topologies for typical voltages employ techniques not suitable for extremely low supply voltages. In this work, single ended and fully differential amplifier topologies for voltage supplies in the range of few hundreds mV were proposed. The proposed approaches use the pseudo differential pairs with the transistor bulk terminals with forward biasing voltages for several purposes, including common mode rejection, output common mode voltage and DC current biasing. Additionally, a ring oscillator based in the same biasing techniques was proposed and designed for two main classes of applications: an intrinsically stable reference oscillator and a voltage controlled oscillator for analog-digital conversion with linearity improvements.

Aplicações móveis que não podem ser recarregadas durante operação, como sensores biomédicos e aplicações da Internet das Coisas, dependem da extração de energia do próprio meio onde se encontram. Tensões de alimentação típicas são normalmente maiores que as disponiveis por métodos de extração de energia do meio e requerem uma conversão de nivel DC que invariavelmente resulta em perdas proporcionais ao fator de conversão. Consequentemente, aplicações projetadas para tensões de alimentação mais próximas da tensão nominal da fonte melhora a eficiência energética. Entretanto, topologias de circuitos elétricos para tensões típicas de alimentação sao impróprias para tensões extremamente baixas. Neste trabalho foram propostas topologias de amplificadores de saída unipolar e diferencial para tensões de alimentaçãoo na casa de centenas de milivolts. As técnicas propostas se baseiam no uso de pares pseudodiferenciais com terminais de corpo polarizados diretamente para vários propósitos, incluindo rejeição de modo comum e polarização de modo comum de saída e corrente DC. Adicionalmente, um oscilador baseado na mesmas técnicas de polarização foi proposto e projetado para duas classes de aplicações: um oscilador de referência intrinsicamente estável e um oscilador controlado por tensão para conversão analógica-digital com melhor linearidade. / Nomadic applications which cannot be recharged while at operation, such as biomedical sensors and Internet of Things applications, rely on energy harvesting from the environment. Typical supply voltages are usually higher than those achieved by energy harvesting methods and requires DC-DC conversion levels, which invariably results in energy loss proportionally to the step of voltage conversion. Consequently, designing at supply voltages closer to the nominal voltage of the energy source improves power efficiency. However, extremely low supply voltages bring design challenges, as circuit topologies for typical voltages employ techniques not suitable for extremely low supply voltages. In this work, single ended and fully differential amplifier topologies for voltage supplies in the range of few hundreds mV were proposed. The proposed approaches use the pseudo differential pairs with the transistor bulk terminals with forward biasing voltages for several purposes, including common mode rejection, output common mode voltage and DC current biasing. Additionally, a ring oscillator based in the same biasing techniques was proposed and designed for two main classes of applications: an intrinsically stable reference oscillator and a voltage controlled oscillator for analog-digital conversion with linearity improvements.

Este trabalho propõe novas topologias de circuitos e técnicas de projeto para filtros ativos e amplificadores de ganho programável (PGA) com operação em ultra baixa tensão (ULV) e ultra-baixa potência (ULP). Os receptores de RF do tipo Bluetooth de baixa energia (BLE), utilizados nos circuitos de internet das coisas (IoT), são as aplicações alvo dos circuitos propostos neste trabalho. Na faixa de ULV são utilizados filtros do tipo RC-ativo, uma vez que possuem uma maior linearidade em relação aos filtros do tipo gmC. A operação em ULP é alcançada neste trabalho utilizando uma nova topologia de amplificador operacional de transcondutância (OTA), com único estágio, que apresenta uma alta eficiência e reduzida sensibilidade às variações de processo, tensão e temperatura (PVT). O baixo ganho de tensão do amplificador de estágio único e os efeitos das cargas resistivas de realimentação são compensados usando um transcondutor negativo, robusto a variações em PVT, conectado às entradas do OTA. A faixa dinâmica dos circuitos é elevada usando topologias totalmente diferenciais e as taxas de rejeição de modo comum e de fonte de alimentação são melhoradas utilizando circuitos de realimentação de modo-comum. Para possibilitar a operação na faixa de ULV todos os circuitos usam apenas dois transistores empilhados e o nível de inversão do canal é elevado através da polarização direta do substrato. Neste trabalho são propostas também uma ferramenta de análise do ponto de operação do transistor, baseando-se na simulação elétrica, e algumas metodologias de projetos para circuitos operando em ULV. Os circuitos e metodologias desenvolvidos foram utilizados para o projeto de um filtro passa-faixa complexo RC-ativo de terceira ordem, um amplificador de ganho programável e um filtro biquadrático do tipo Tow-Thomas com ganho programável, compatíveis com receptores de RF do padrão BLE. Para a implementação do PGA, uma nova topologia de transconductor negativo programável foi desenvolvida para permitir a compensação ótima do amplificador operacional em todos os modos de ganho. Todos os circuitos foram projetados para operar com uma tensão de alimentação de 0,4 V e foram prototipados em processos de fabricação CMOS e BiCMOS de 180 nm e 130 nm, respectivamente. Os resultados experimentais e de simulação pós-layout demonstram uma operação adequada em 0,4 V, uma ultra-baixa dissipação de potência, atingindo o mínimo de 10.9 ?W/polo, e a melhor figura-de-mérito (FoM) em relação aos outros filtros ativos e amplificadores disponíveis na literatura. / This thesis proposes novel circuit topologies and design techniques of ultra-low voltage (ULV) and ultra-low power (ULP) active-filters and programmable gain amplifiers (PGA) suitable for the Bluetooth low energy (BLE) RF receivers used in the Internet of Things (IoT) applications. The active-RC filters are preferred to the gm-C topologies at the ULV operation due to its improved linearity. However, the closed-loop operation increases the operational amplifier required voltage gain and its capacity to drive the resistive feedback load. In this work, the ULP dissipation is obtained by proposing a very efficient single-stage inverter-based operational transconductance amplifier (OTA) and a proper forward bulk biasing to reduce the sensitivity to process, voltage and temperature (PVT) variations. The low voltage gain and the resistive load effects on the single-stage OTA are completely compensated by using a PVT robust negative transconductor connected at the OTA inputs. The dynamic range is increased by using fully-differential topologies and common-mode feedback to improve the common-mode and power supply rejection rates. The operation at the ULV range is reached by using only two-stacked transistors in all the circuit implementations and bulk forward bias in some transistors to reduce the threshold voltage and to increase the channel inversion level. An operation point simulation-based tool and some design methodologies are also proposed in this work to design the ULV circuits. The proposed circuits were used to design a third-order active-RC complex band-pass filter (CxBPF), a programmable gain amplifier (PGA) and a Tow-Thomas biquad, with integrated programmable gain capability, suitable for BLE RF receivers. The PGA implementation uses a new programmable input negative transconductor to obtain the optimal closed-loop amplifier compensation in all the gain modes. The circuits were designed to operate at the power supply voltage of 0.4 V and are prototyped in 180 nm and 130 nm low-cost CMOS and BiCMOS process, respectively. The experimental and post-layout simulation results have demonstrated the proper ULV operation at 0.4 V, the ultra-low power dissipation down to 10.9 ?W/pole and the best figure-of-merit (FoM) among the state-of-the-art active-filters and amplifiers from the literature.

Αντικείμενο της διπλωματικής εργασίας είναι η σχεδίαση ενός βιοϊατρικού συστήματος που είναι κατάλληλο για την ανίχνευση εμβοών σε ασθενείς. Το σύστημα αυτό αποτελείται από ένα αναλογικό τμήμα το οποίο περιλαμβάνει τους εξαγωγείς ενέργειας ζώνης συχνοτήτων για τα alpha, gamma και theta waves του εγκεφάλου που τροφοδοτούν τα αντίστοιχα κανάλια του συστήματος. Επίσης, το σύστημα περιλαμβάνει και ένα ψηφιακό τμήμα αποτελούμενο από συγκριτές ρεύματος και μια πύλη AND και το οποίο θα χρησιμεύσει για την λήψη της απόφασης σχετικά με το αν πάσχει ή όχι ο ασθενής. Η έξοδος του συστήματος θα οδηγεί ένα σύστημα ανάδρασης, ο οποίος θα προσαρμόζει τα επίπεδα έντασης των αντίστοιχων σημάτων που δέχεται ο ασθενής για την αποφυγή της εμφάνισης του φαινομένου της εμβοής. Η υλοποίηση του συστήματος γίνεται με χρήση MOS transistors τα οποία λειτουργούν στην περιοχή υποκατωφλίου. Η χρήση μικρών ρευμάτων πόλωσης δίνει τη δυνατότητα για σχεδίαση συστημάτων με χαμηλή κατανάλωση ισχύος και ταυτόχρονα επιτρέπει την υλοποίηση μεγάλων τιμών αντιστάσεων, οι οποίες είναι απαραίτητες για την πραγματοποίηση μεγάλων σταθερών χρόνου που απαιτούνται για τη διαχείριση των χαμηλής συχνότητας βιοϊατρικών σημάτων. Στόχος της διπλωματικής εργασίας είναι η ανάπτυξη πρωτότυπης τοπολογίας για το αναλογικό τμήμα του συστήματος. Αυτό επιτεύχθηκε με την ανάπτυξη νέων δομών φίλτρων τα οποία λειτουργούν στο πεδίο του υπερβολικού ημιτόνου. Οι κύριοι λόγοι υιοθέτησης αυτής της τεχνικής είναι ότι προσφέρει ταυτόχρονα τα παρακάτω: (α) δυνατότητα επεξεργασίας σημάτων τα οποία είναι μεγαλύτερα από το ρεύμα πόλωσης, λόγω της ενσωματωμένης λειτουργίας σε τάξη-ΑΒ, (β) δυνατότητα λειτουργίας με καλή γραμμικότητα σε πολύ χαμηλή τάση τροφοδοσίας, (γ) ηλεκτρονική ρύθμιση των συχνοτικών χαρακτηριστικών τους από το ρεύμα πόλωσης, (δ) υλοποίηση φίλτρων χωρίς αντιστάτες, (ε) υλοποίηση φίλτρων με χρήση μόνο γειωμένων πυκνωτών. Η σχεδίαση των κυκλωμάτων, τόσο σε επίπεδο σχηματικού, όσο και σε επίπεδο μασκών, έγινε με τη χρήση του λογισμικού Cadence και με το Design Kit που παρέχεται από την τεχνολογία AMS CMOS C35 0.35μm. Συγκρινόμενη με την αντίστοιχη ήδη προταθείσα δομή ανιχνευτή εμβοών, η προτεινόμενη τοπολογία προσφέρει τα παρακάτω ελκυστικά χαρακτηριστικά: (α) μειωμένη κατανάλωση ισχύος και (β) λειτουργία του αναλογικού τμήματος σε μικρότερη τάση τροφοδοσίας (0.5V). / Subject of this M. Sc.Τhesis is the design of a biomedical system that is suitable for detecting tinnitus in patients. This system consists of an analog subsystem comprising band energy extractors for alpha, gamma and theta waves of the EEG that feed the channels of the system. The system also includes a digital section composed of current comparator and AND gate, which will serve as a decision on whether or not the suffering patient. The output of the system will drive a feedback system, which will adjust the intensity levels of the respective signals received by the patient to prevent the occurrence of the phenomenon of tinnitus. The system implementation is done using MOS transistors operating in the subthreshold region. The use of low-level bias currents allows for system design with low power consumption and, simultaneously, enables the implementation of large values of resistors that are necessary for the realization of large time constants required for the handling of low frequency biomedical signals. The aim of this thesis is to develop novel topology for the analog subsystem. Tjhis was achieved through the development ddevelopment of novel structures of filters using the concept of filtering in the Sinh-Domain. The main reasons for using this technique is that it simultaneously offers the following attractive characteristics: (a) capability for processing signals which are larger than the bias current, due to the inherent class-AB operation, (b) ability to achieve a relative high linearity at very low power supply voltage, (c) electronic adjustment of frequency characteristics through the bias current, (d) implementation of filters without resistors, and (e) implementation of filters using only grounded capacitors. The design of circuits, both at schematic and post-layout levels was performed using the Cadence software and the Design Kit provided by the AMS CMOS C35 0.35μm technology. Compared with the corresponding already proposed structure tinnitus detector, the proposed topology to offer the following attractive features: (a) reduced power consumption, and (b) operation of the analog section in lower supply voltage (0.5V).

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.