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Ph.D. / Electrical Engineering / Nanometer-scale devices have attracted great attention as the ultimate evolution of silicon integrated circuit technology. However, fabrication of nanometer-scale silicon based devices has met great difficulty because it places severe constraints on process technology. This is especially true for SiGe/Si heterostructures because they are particularly sensitive to strain relaxation and/or process induced defects. Recently developed Pulsed Laser Induced Epitaxy (PLIE) offers a promising approach for the fabrication of nanometer- scale SiGe/Si devices. It possesses the advantage of ultra-short time, low thermal budget and full compatibility with current silicon technology. The selective nature of the process allows epitaxial growth of high quality, localized SiGe layers in silicon. In this thesis, a process to fabricate SiGe nanowires in silicon using PLIE is described. In particular, Ge nanowires with a cross-section of ~6 x 60 nm² are first formed using a lift-off process on the silicon substrate with e-beam lithography, followed by a thin low-temperature oxide deposition. Defect-free SiGe nanowires with a cross-section of ~25 x 95 nm² are then produced by impinging the laser beam on the sample. We thus demonstrate PLIE is a suitable fabrication technique for SiGe/Si nanostructures. Fabrication of Ge nanowires is also studied using Focused Ion Beam (FIB) micromachining techniques. Based on the SiGe nanowire process, we propose two advanced device structures, a quantum wire MOSFET and a lateral SiGe Heterojunction Bipolar Transistor (HBT). MEDICI simulation of the lateral SiGe HBT demonstrates high performance of the device. In order to characterize the SiGe nanowires using cross-sectional transmission electron microscopy, an advanced versatile focused ion beam assisted sample preparation technique using a multi-layer stack scheme for localized surface structures is developed and described in this thesis.

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Yeung Wing-ki. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 64-65). / Abstracts in English and Chinese. / Abstracts --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Contents --- p.v / List of Figures --- p.vii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Low ower Design --- p.1 / Chapter 1.2. --- ower Consumtion in Conventional CMOS Logic --- p.2 / Chapter 1.3. --- Adiabatic Switching --- p.7 / Chapter 1.3.1. --- Varying Suly Voltage --- p.7 / Chapter 1.3.2. --- Charge Recovery --- p.12 / Chapter 2. --- Adiabatic Quasi-static CMOS Logic --- p.13 / Chapter 2.1. --- AqsCMOS Logic Building Block --- p.14 / Chapter 2.2. --- AqsCMOS inverter --- p.17 / Chapter 2.3. --- ower Reduced in Sinusoidal Suly --- p.18 / Chapter 2.4. --- Clocking Scheme --- p.21 / Chapter 3. --- Contactless Smart Card --- p.23 / Chapter 3.1. --- Architecture --- p.23 / Chapter 3.2. --- Standardization --- p.26 / Chapter 3.3. --- Universal Asynchronous Receiver and Transmitter (UART) --- p.30 / Chapter 4. --- Clock Recovery --- p.35 / Chapter 4.1 --- Adiabatic Ring Oscillator --- p.35 / Chapter 4.2. --- Secial Frequencies of AqsCMOS Ring Oscillator --- p.39 / Chapter 4.3. --- ower Extraction --- p.41 / Chapter 5. --- Evaluations and Measurement Results --- p.43 / Chapter 5.1. --- Outut Transitions --- p.43 / Chapter 5.2. --- Ring Oscillator --- p.44 / Chapter 5.3. --- Synchronization --- p.47 / Chapter 5.4. --- ower Consumtion --- p.49 / Chapter 6. --- Conclusion --- p.53 / Aendix --- p.54 / Glossary --- p.62 / Reference --- p.64

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