Thin film copper, indium, gallium, selenide (CIGS) solar cells are promising in the field of photovoltaic technology. To reduce material and fabrication cost, as well as increasing electrical properties of the cell, research is ongoing towards ultra-thin film solar cells (absorption layer thickness less than 500 nm). Ultra-thin CIGS solar cells has shown a decrease in interface recombination and improved optical properties when adding a rear contact passivation layer of aluminium oxide. In this work, the process of creating sub-micrometer features of a passivation layer using conventional optical lithography is investigated. To specify, the objective was to optimize the development conditions in the optical lithography process when fabricating equidistant line contacts in aluminium oxide with 800 nm feature size. It was found that line contacts with smaller feature sizes require longer development time, than line contacts with larger feature sizes. The experiments conducted showed that the pre-set development and exposure conditions used by the NOA group are not optimized for 800 nm or smaller line contacts. Further, for the optical lithography process, silicon substrates are not comparable with substrates of soda lime glass coated with molybdenum. Slight underdevelopment of a sample, showed line contacts smaller than the resolution of the laser used in the exposure – suggesting an alternative method of processing small line contacts with optical lithography.

Durant les 5 dernières décennies, les technologies CMOS se sont imposées comme méthode de fabrication principale pour les circuits semi-conducteurs intégrés avec notamment le transistor MOSFET. Néanmoins, la miniaturisation de ces transistors en technologie CMOS sur substrat massif atteint ses limites et a donc été arrêtée. Les filières FDSOI apparaissent comme une excellente alternative permettant une faible consommation et une excellente maîtrise des effets électrostatiques dans les transistors MOS, même pour les nœuds technologiques 14 et 28 nm. Cependant, la pente sous le seuil (60 mV/décade) du MOSFET ne peut pas être améliorée, ce qui limite la réduction de la tension d’alimentation. Cette restriction a motivé la recherche de composants innovants pouvant offrir des déclenchements abrupts tels que le Z2-FET (Zéro pente sous le seuil et Zéro ionisation par impact), Z2-FET DGP (avec double Ground Plane) et Z3-FET (Zéro grille avant). Grace à leurs caractéristiques intéressantes (déclenchement abrupte, faible courant de fuite, tension de déclenchement ajustable, rapport de courant ION/IOFF élevé), les dispositifs à modulation de bandes peuvent être utilisés dans différentes applications. Dans ce travail, nous nous sommes concentrés sur la protection contre les décharges électrostatiques (ESD), la mémoire DRAM embarquée sans capacité de stockage, et les interrupteurs logiques. L’étude des mécanismes statique et transitoire ainsi que des performances de ces composants a été réalisée grâce à des simulations TCAD détaillées, validées systématiquement par des résultats expérimentaux. Un modèle de potentiel de surface pour les trois dispositifs est également fourni. / During the past 5 decades, Complementary Metal Oxide Semiconductor (CMOS) technology was the dominant fabrication method for semiconductor integrated circuits where Metal Oxide Semiconductor Field Effect Transistor (MOSFET) was and still is the central component. Nonetheless, the continued physical downscaling of these transistors in CMOS bulk technology is suffering limitations and has been stopped nowadays. Fully Depleted Silicon-On-Insulator (FDSOI) technology appears as an excellent alternative that offers low-power consumption and improved electrostatic control for MOS transistors even in very advanced nodes (14 nm and 28 nm). However, the 60 mV/decade subthreshold slope of MOSFET is still unbreakable which limits the supply voltage reduction. This motivated us to explore alternative devices with sharp-switching: Z2-FET (Zero subthreshold slope and Zero impact ionization), Z2-FET DGP (with Dual Ground Planes) and Z3-FET (Zero front-gate). Thanks to their attractive characteristics (sharp switch, low leakage current, adjustable triggering voltage and high current ratio ION/IOFF), band-modulation devices are envisioned for multiple applications. In this work, we focused on Electro-Static Discharge (ESD) protection, capacitor-less Dynamic Random Access Memory and fast logic switch. The DC and transient operation mechanisms as well as the device performance are investigated in details with TCAD simulations and validated with systematic experimental results. A compact model of surface potential distribution for all Z-FET family devices is also given.