Two kinds of companding filters are presented in this dissertation. The first one is a square-root domain filter based on operational transconductance amplifier (OTA). This one is compact and simple. The total are of the circuit excluding pads is 0.013 mm2. The supply voltage is 1.5V and the cutoff frequency can be tuned from 1.1 kHz to 35.2 kHz when the external capacitance C is 1nF. The total harmonic distortions is 0.93% and the power consumption is 152.29 £gW for a 10£gA DC input current. The other one is a tunable log-domain filter. The log domain filters uses parasitic vertical bipolar junction transistor (VBJT) in standard CMOS process for high frequency. The cut-off frequency is from 8.6 MHz to 25.8 MHz and the power dissipation is 585 £gW. All experimental results in a TSMC 0.35 £gm 2P4M CMOS process confirm the feasibility of the methodology.