Two kinds of companding filters are presented in this dissertation. The first one is a square-root domain filter based on operational transconductance amplifier (OTA). This one is compact and simple. The total are of the circuit excluding pads is 0.013 mm2. The supply voltage is 1.5V and the cutoff frequency can be tuned from 1.1 kHz to 35.2 kHz when the external capacitance C is 1nF. The total harmonic distortions is 0.93% and the power consumption is 152.29 £gW for a 10£gA DC input current. The other one is a tunable log-domain filter. The log domain filters uses parasitic vertical bipolar junction transistor (VBJT) in standard CMOS process for high frequency. The cut-off frequency is from 8.6 MHz to 25.8 MHz and the power dissipation is 585 £gW. All experimental results in a TSMC 0.35 £gm 2P4M CMOS process confirm the feasibility of the methodology.

Conventional gm-c filters have limited voltage swings in low voltage operation. CMOS companding filters replace gm-c filters in low voltage environment for high dynamic range. The square-root domain filter and log-domain filter belongs to this companding filter category. In this thesis, a second order low pass square root domain filter (SRD filter) based on the up-down TL (translinear loop) circuit structure is presented. The SRD filter consists of four geometric-mean cells and three squarer/divider cells. The advantages of the proposed circuits are low supply voltage, low power consumption, high bandwidth, and low total harmonic distortion (THD). The circuit has been fabricated with 0.35£gm CMOS technology. It operates with a supply voltage of 1.5V, and the bias current varies from 0.5£gA to 30£gA. Measurement results show that the cutoff frequency can be tuned from 3.12MHz to 8.11MHz when the Capacitance (C) is 5pF.The total harmonic distortion is 0.28%, and the power consumption is 1.09mW.