Submitted by Lara Oliveira (lara@ufersa.edu.br) on 2017-09-11T22:44:19Z No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-10-27T13:04:28Z (GMT) No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Approved for entry into archive by Vanessa Christiane (referencia@ufersa.edu.br) on 2017-10-27T13:07:44Z (GMT) No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) / Made available in DSpace on 2017-10-27T13:10:30Z (GMT). No. of bitstreams: 1 AllysonALF_DISSERT.pdf: 2286744 bytes, checksum: 6ff716a2c28bcb7db9ac2c2775cefd83 (MD5) Previous issue date: 2017-08-25 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Along with the need to develop controllers for industrial processes, it arises the need to study advanced control techniques, such as fuzzy controllers, that can supply nonlinearities inherent in the systems. The implementation of these fuzzy controllers based on Hardware Description Language (HDL) has the advantage of high speed and fast reprogramming for use in another project, by changing only desired variables. The objective of this study is to develop a fuzzy controller implemented in VHDL (Very High Speed Integrated Circuit Hardware Description Language) for a tank level system and to evaluate its effectiveness, comparing it with a fuzzy controller developed in Matlab®. Its methodology is to develop a fuzzy system described in VHDL and divided into coding, inference and decoding for a Quanser cylindrical tank system and another system with a trapezoidal format tank. The results of this proposal were satisfactory given the limitations presented by the system / Com a necessidade de desenvolver controladores para processos industriais, surge a necessidade de estudar técnicas de controle avançado, como por exemplo, controladores fuzzy, que possam suprir não linearidades inerentes nos sistemas. A implementação destes controladores fuzzy baseados em Linguagem de Descrição de Hardware (HDL) tem como vantagem a alta velocidade e a reprogramação rápida para utilização em outro projeto, alterando apenas variáveis desejadas. O objetivo do trabalho é desenvolver um controlador fuzzy implementado em VHDL (Very High Speed Integrated Circuit Hardware Description Language) para um sistema de nível de tanques e avaliar sua eficácia, comparando-o com um controlador fuzzy desenvolvido em Matlab®. Sua metodologia consiste em desenvolver um sistema fuzzy descrito em VHDL e divididos em codificação, inferência e decodificação para um sistema de tanque cilíndrico da Quanser e outro sistema com tanque de formato trapezoidal. Os resultados desta proposta se mostraram satisfatórios diante de limitações apresentadas pelo sistema / 2017-09-11

The modern embedded system is getting more complicated due to the functional requirements of the system are rapidly increasing. The modern system must have more reliable, as it deals with a lot of data. The distributed systems are used in variety technologies field due to it has more reliable than single control unit. It can transfer task to other processing unit when the one part of system failed while the single control unit failed cause the system to stop operate. The FPGA are being used increasingly in the distributed system due to the benefit of FPGA over microcontroller and ASIC. FPGA is flexible than ASIC due to the ability to reconfiguration its function. FPGA processes the data in parallel, therefore, it computes the data faster than the microcontroller that computes the data in concurrence. The flexibility of FPGA supports the development of reliable distributed system. When one of FPGA failed, the other FPGA can reconfiguration itself to operate on the task of the failed FPGA. The method to reconfigure the FPGA structure is a process of loading new bitstream file into FPGA. For generating variety configurations of distributed system. The developer must develop number of bitstream file according to number of reconfiguration designs. Although the FPGA is flexible and can reconfiguration anytime, the development process of configuration file is a redundancy workload. One FPGA design structure equals one configuration file. This project focus on reduce the redundancy workload, therefore, it can reduce the development time and make the development project launching faster. This virtual partial reconfiguration framework is developed to assist the developer in generating many configuration files without coding. The framework will determine all possible combination of modules and generates all combination design files. One set of the design contain the VHDL file and UCF file. The developer can use these files to synthesise in FPGA vendor development tool and generate bitstream. This virtual partial reconfiguration framework also provides the partial reconfiguration benefits except runtime reconfiguration.