Spelling suggestions: "subject:"VHDL core generator""
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Design and Implementation of Sampling Rate Converters for Conversions between Arbitrary Sampling RatesMerkelov, Fedor, Kodess, Yaroslav January 2004 (has links)
In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.
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Design and Implementation of Sampling Rate Converters for Conversions between Arbitrary Sampling RatesMerkelov, Fedor, Kodess, Yaroslav January 2004 (has links)
<p>In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. </p><p>This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. </p><p>The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. </p><p>The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.</p>
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