<p>As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA.</p><p>This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA.</p><p>The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.</p>

As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA. This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA. The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.

CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior / This work presents a new structure for an all-digital BPSK demodulator developed for space communications that performs simultaneously the sampling and down-conversion of the the intermediate frequency signal to the baseband signal. The most important aspect of this work is the design of a new interpolator to retrieve lost samples during the down conversion process, and also to simplify the demodulator implementation. This interpolator correlates the samples of the output signal in such way that it was necessary to design a optimum &#64257;lter appropriate to process the samples corrupted by gaussian and colored noise. The effects of the new interpolation at the noise are analyzed as well as the way it affects the whole demodulator performance. After performing the optimum &#64257;ltering, the phase and symbol offsets are estimated and corrected. For the phase, for example, it was used a DPLL (Digital Phase Locked Loop), a digital variation of the PLL, a well known structure and largely utilized in analogical electronics. The DPLL is a closed-loop structure that estimates and corrects the values for the angular which corresponds to the phase deviation caused by the offset between the transmitter and receiver oscilators. For the timing parameter estimation, it was used the Oerder&Meyer estimator that is the digital equivalent to the well known square timing recovery structure. After that, the correction is performed by an interpolation operation over the samples of the received signal, where a &#64257;lter, named Farrow &#64257;lter, is applied to these samples, calculating the new samples of that signal at the corrected time instants. This system is mathematically described, all the signals expressions of every stage of the demodulator are analyzed, including the noise statistics. Some computational simulation results are shown and the performance degradation is discussed. / Este trabalho apresenta um modelo de demodulador que realiza simultaneamente a conversÃo analÃgico-digital e a conversÃo em frequÃncia por amostragem em banda passante de um sinal com modulaÃÃo BPSK (Binary Phase Shift Keying) para aplicaÃÃo em enlaces espaciais. O aspecto mais importante do trabalho foi o desenvolvimento de uma nova operaÃÃo de interpolaÃÃo para recuperaÃÃo das amostras perdidas na conversÃo de frequÃncia e que simpli&#64257;ca a implementaÃÃo do demodulador. O interpolador correlaciona as amostras do sinal de forma que torna-se necessÃrio o projeto de um &#64257;ltro Ãtimo apropriado para processar as amostras corrompidas e mitigar os efeitos do ruÃdo gaussiano e colorido. Os efeitos deste novo interpolador no ruÃdo sÃo analisados, assim como a forma em que ele afeta a performance do sistema. ApÃs a &#64257;ltragem Ãtima, segue a correÃÃo dos erros de sincronismo de atraso de simbolo e de fase. Para a recuperaÃÃo do sincronismo de fase foi utilizado um DPLL (Digital Phase Locked Loop), uma variante digital de uma estrutura bastante conhecida e utilizada em eletrÃnica analÃgica. O DPLL à uma estrutura em malha fechada que estima e corrige os valores do desvio angular das amostras, o que corresponde ao devio provocado pela diferenÃa de fase entre os osciladores do transmissor e do receptor. Para a recuperaÃÃo do atraso de sÃmbolo foi utilizada, para estimaÃÃo do tempo de atraso, o estimador de Oerder&Meyer que à o equivalente digital da conhecida recuperaÃÃo de temporizaÃÃo em tempo contÃnuo com a lei quadrÃtica. ApÃs a estimaÃÃo ser realizada, à feita a correÃÃo deste atraso nas amostras do sinal recebido atravÃs de uma operaÃÃo de interpolaÃÃo, onde novos valores do sinal sÃo calculados para os instantes de tempo corrigidos. Essa operaÃÃo à realizada por um &#64257;ltro interpolador, uma estrutura especial conhecida como estrutura de Farrow. O sistema proposto foi descrito matematicamente, sendo analisadas as expressÃes dos sinais nos diferentes estÃgios do conversor, bem como as estatÃsticas dos sinais de ruÃdo. Apresentam-se os resultados da simulaÃÃo computacional nos quais se avalia a perda no desempenho do demodulador, analisando suas causas.

A number of routine painful procedures such as castration and tail-docking are currently performed in swine production without the benefit of anaesthesia or analgesia. In addition, parturition is generally considered painful. Providing analgesics at the time of castration and tail-docking lowered plasma cortisol levels of the piglets suggesting a reduction in pain associated with the procedures. The use of the non-steroidal antiinflammatory drug meloxicam also resulted in less isolated behaviour of male piglets following castration. Providing meloxicam routinely following parturition did not result in reduced neonatal mortality or piglet growth, but lowered plasma cortisol suggesting a reduction in pain. Producers in the future may need to consider using pain control as part of their standard operating procedures in order improve piglet welfare and meet their consumers’ expectations, but are unlikely to see an economic return associated with improved productivity. / Please do not reject this before tomorrow afternoon. I am going to stop by the Office of Graduate Studies and hand in the necessary documents. / Boehringer Ingelheim (Canada) Ltd. and Ontario Pork

In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.

<p>In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. </p><p>This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. </p><p>The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. </p><p>The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.</p>

Modern signal processing applications emerging in telecommunication and instrumentation industries have placed an increasing demand for ADCs with higher speed and resolution. The most fundamental challenge in such a progress lies at the heart of the classic signal processing: the Shannon-Nyquist sampling theorem which stated that when sampled uniformly, there is no way to increase the upper frequency in the signal spectrum and still unambiguously represent the signal except by raising the sampling rate. This thesis is dedicated to the exploration of the ways to break through the Shannon-Nyquist sampling rate by applying non-uniform sampling techniques. Time interleaving is probably the most intuitive way to parallel the uniform sampling process in order to achieve a higher sampling rate. Unfortunately, the channel mismatches in the TIADC system make the system an instance of a recurrent non-uniform sampling system whose non-uniformities are detrimental to the performance of the system and need to be calibrated. Accordingly, this thesis proposed a flexible and efficient architecture to compensate for the channel mismatches in the TIADC system. As a key building block in the calibration architecture, the design of the Farrow structured adjustable fractional delay filter has been investigated in detail. A new modified Farrow structure is proposed to design the adjustable FD filters that are optimized for a given range of bandwidth and fractional delays. The application of the Farrow structure is not limited to the design of adjustable fractional delay filters. It can also be used to implement adjustable lowpass, highpass and bandpass filters as well as adjustable multirate filters. This thesis further extends the Farrow structure to the design of filters with adjustable polynomial phase responses. Inspired by the theory of compressive sensing, another contribution of this thesis is to use randomization as a means to overcome the limit of the Nyquist rate. This thesis investigates the impact of random sampling intervals or jitters on the power spectrum of the sampled signal. It shows that the aliases of the original signal can be well shaped by choosing an appropriate probability distribution of the sampling intervals or jitters such that aliases can be viewed as a source of noise in the signal power spectrum. A new theoretical framework has been established to associate the probability mass function of the random sampling intervals or jitters with the aliasing shaping effect. Based on the theoretical framework, this thesis proposes three random sampling architectures, i.e., SAR ADC, ramp ADC and level crossing ADC, that can be easily implemented based on the corresponding standard ADC architectures. Detailed models and simulations are established to verify the effectiveness of the proposed architectures. A new reconstruction algorithm called the successive sine matching pursuit has also been proposed to recover a class of spectrally sparse signals from a sparse set of non-uniform samples onto a denser uniform time grid so that classic signal processing techniques can be applied afterwards.

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