Η απεικόνιση και συμπίεση χωρικών δεδομένων έχει γίνει ένα θέμα έμφασης και προσοχής για τον τομέα των computer graphics και για εφαρμογές επεξεργασίας εικόνας. Τα quadtrees, σαν μία από τις ιεραρχικές δομές δεδομένων, βασιζόμενα στην αρχή του επαναλαμβανόμενου διαχωρισμού του χώρου, προσφέρουν πάντα μία συμπαγή και αποτελεσματική αντιπροσώπευση μίας εικόνας. Ο σκοπός αυτής της εργασίας είναι η ανάλυση του αλγορίθμου quadtree, και η σχεδίαση του αλγορίθμου με γλώσσα VHDL. Αναλύεται η μηχανή καταστάσεων και το datapath του υπό ανάπτυξη κυκλώματος. Επίσης παρουσιάζονται κυματομορφές των σημάτων της κάθε κατάστασης από την προσομοίωση που έγινε στο Modelsim. Για την επιβεβαίωση της λειτουργίας του κυκλώματος, έγινε σύνθεση του κυκλώματος με τη βοήθεια του προγράμματος ISE της Xilinx. Όσον αφορά την υλοποίηση, χρησιμοποιήθηκε το board της Xilinx Virtex-5 FPGA ML 507 και εξομοίωση λειτουργίας για εικόνα μεγέθους 64x64. Στο Παράρτημα παρουσιάζονται ο κώδικας Matlab της συνάρτησης qtdecomp που χρησιμοποιήθηκε για την κατανόηση του αλγόριθμου quadtree και καθώς και ο κώδικας Matlab που δημιουργήθηκε για να επαληθεύσει τα αποτελέσματα της προσομοίωσης με Modelsim. / Compression of spatial data has become a matter of emphasis and attention in the field of computer graphics and image processing applications. The quadtrees, as one of the hierarchical data structures, applies the principle of repetitive decomposition of space and offers a compact and efficient representation of an image. The purpose of this paper is to analyze the algorithm quadtree, and to design the algorithm with the language VHDL. In this paper the state machine is analyzed as well as the datapath of the circuit. Furthermore the waveforms of the control signals for each state are presented from the simulation done in the Modelsim environment. A confirmation of the operation of the circuit took also place.The circuit was composed with the help of the ISE of Xilinx. Regarding the implementation, the board of Xilinx Virtex-5 FPGA ML 507 is used and the emulation is done for a picture sized 64x64. The Annex outlines code of the MATLAB function qtdecomp used for understanding the quadtree algorithm and the Matlab code created to verify the simulation results of Modelsim.

The main part of the digital application is its user interface. Users can check the status of the programme or change its state. There are many ways to obtain a suitable interface. During the design stage the simplest interface is chosen that provides the necessary functions. In most cases the interface contains a display. This diploma thesis deals with the design of an extension board to plug in a display to a programmable device, a control algorithm for the display and the design of a simple display interface. There are two ways to design software. The first of them is achieved by the processor PicoBlaze, which contains all the required functions. The second solution is by the state machine written in VHDL language. Both solutions can be used in the same way, but the latter solution is quicker and requires less hardware resources.

Στόχος της παρούσας Διπλωματικής Εργασίας είναι ο σχεδιασμός και υλοποίηση ενός Κρυπτογραφικού Συστήματος με βάση τον Αλγόριθμο κατακερματισμού JH. Ο σχεδιασμός του κρυπτογραφικού αυτού συστήματος έγινε με τη χρήση γλώσσας VHDL (Very High Speed Integrated Circuits hardware description language) και στη συνέχεια η υλοποίηση αυτή έγινε πάνω σε πλατφόρμα FPGA (Field Programmable Gate Array). Ο αλγόριθμος JH είναι ένας αλγόριθμος κατακερματισμού (hash function) ο οποίος σχεδιάστηκε στα πλαίσια του διαγωνισμου κρυπτογραφιας NIST (National Institute of Standards and Technology). Η πρώτη του έκδοση έγινε στις 31 Οκτωβρίου 2008 ενώ η τελική του έκδοση έγινε στις 16 Ιανουαρίου 2011. Ο Αλγόριθμος JH έχει τρεις υποκατηγορίες. Υπάρχει ο JH-224, JH-256, JH-384 και ο JH-512. Βασικό χαρακτηριστικό του αλγορίθμου αυτού είναι το γεγονός πώς οι λειτουργίες που συμβαίνουν σε κάθε γύρο είναι ίδιες. Επίσης σημαντικό γνώρισμα ειναι η ασφάλεια που παρέχει ο αλγόριθμος αυτός καθώς ο μεγάλος αριθμός των ενεργών S-boxes που χρησιμοποιούνται και ταυτόχρονα το γεγονός ότι σε κάθε γύρο χρησιμοποιείται ένα διαφορετικό κλειδι το οποίο παράγεται εκεινη τη στιγμή και δεν ειναι αποθηκευμένο σε ένα σημείο, στο οποίο θα μπορούσε κάποιος να επέμβει, κάνει το σύστημά μας εξαιρετικά δυνατό και ανθεκτικό απέναντι σε επιθέσεις όπως είναι η διαφορική κρυπτανάλυση. Για την εξακρίβωση της ορθής λειτουργίας του συστήματος χρησιμοποιήθηκε μία υλοποίηση του Αλγορίθμου JH σε γλώσσα C. Χρησιμοποιώντας την υλοποίηση αυτή κάθε φορά που θέλουμε να κρυπτογραφήσουμε ένα μήνυμα το οποίο είναι μία σειρά από bit, λαμβάνουμε το κρυπτογραφημένο μήνυμα. Αυτο το κρυπτογραφημένο μήνυμα το συγκρίνουμε με αυτό που παίρνουμε στην έξοδο του συστήματος JH που σχεδιάσαμε και με αυτό το τρόπο επιβεβαιώνουμε την ορθότητα του αποτελέσματος. Ύστερα από την non-pipelined υλοποίηση του συστήματος αυτού, χρησιμοποιήθηκε η τεχνική της συσωλήνωσης (pipeline). Πιο συγκεκριμένα εγιναν 4 διαφορετικές pipelined υλοποιήσεις με 2,3,6 και 7 στάδια. Σκοπός είναι για κάθε μία pipelined υλοποίηση να γίνει έλεγχος σε θέματα απόδοσης, κατανάλωσης ισχύος καθώς επίσης και σε θέματα επιφάνειας. Στη συνέχεια γίνεται μία σύγκριση στα προαναφερθέντα θέματα μεταξύ των διαφορετικών pipelined υλοποιήσεων και με την non-pipelined υλοποίηση του κρυπτογραφικού συστήματος JH. Επίσης αξίζει να σημειωθεί πώς γίνεται ιδιαίτερη αναφορά στο throughput και στο throughput per area των pipelined υλοποιήσεων. Από τα πειραματικά αποτελέσματα που προέκυψαν η JH NON PIPELINED υλοποίηση έχει απόδοση 97 MHz με κατανάλωση ισχύος 137mW και συνολική επιφάνεια 2284 slices σε SPARTAN 3E FPGA συσκευή. Ενώ από την ανάλυση της JH NON PIPELINED υλοποίησης και των 4 pipelined υλοποιήσεων σε 4 διαφορετικά FPGA (2 της οικογένειας SPARTAN και 2 της οικογένειας VIRTEX) συμπεραίνουμε πώς στην οικογένεια VIRTEX η κατανάλωση ισχύος είναι πάντα μεγαλύτερη σε σχεση με την οικογένεια SPARTAN. / The purpose of this Thesis Project is the design and implementation of a Cryptographic System using the JH Hash Algorithm. The design of this Cryptographic System was performed using the VHDL language (Very High Speed Integrated Circuits hardware description language) and then this implementation was executed on a FPGA platform (Field Programmable Gate Array).The JH Algorithm is a hash algorithm that was developed during the NIST (National Institute of Standards and Technology) Cryptography Competition. Its first version was released on 31 October 2008 while its last version was released on 16 January 2011. The JH Hash Algorithm has three subcategories. There is JH-224, JH-256, JH-384, and JH-512. Basic characteristic of this Algorithm is the fact that the functions that are executed in each round are identical. Moreover important characteristic is the security that this Algorithm provides us while the big number of active S-Boxes that is used and in the same time the fact that in each round a different key is produced on the fly, and is not stored in a place that a third person could have access, makes our system really strong and resistant to attacks such as the differential attack. To confirm the right functionality of the system the implementation of the JH Algorithm in C Language is used. Using this implementation each time we want to cipher a message, which is a sequence of bits, we get the message digest. This message digest is compared with the message digest that we get from the JH system that we developed with VHDL and in this way we confirm the correctness of the result. After the non pipelined implementation of the JH system the pipeline technique was used. To be more specific 4 different pipelined implementations with 2, 3, 6 and 7 stages were performed. The target was to check the performance, area and power dissipation for each pipelined implementation. Next a comparison was performed between the various pipelined implementations and the non pipelined implementation for the above mentioned issues. In addition to this it is worth to mention that considerable reference is made for throughput and throughput per area for the pipelined implementations. According to the experimental results the JH NON PIPELINED implementation has a performance of 97 MHz, with power dissipation of 137mW and a total area of 2284 Slices on SPARTAN 3E FPGA device. From the JH NON PIPELINED implementation and the other 4 pipelined implementations on 4 different FPGA Devices (2 from the VIRTEX family and 2 from the SPARTAN family) we concluded that the power dissipation is bigger in VIRTEX family devices in comparison to SPARTAN family Devices.

Resumo: Este trabalho trata da análise, desenvolvimento e implementação de um estágio Pré- Regulador Retificador Boost de alto fator de potência, para servir como fonte de alimentação para sistemas de iluminação fluorescente multi-lâmpadas, com potência de até 1.200 watts e com índices de qualidade tanto para a fonte de alimentação em corrente alternada quanto para o sistema de iluminação. Este conversor será controlado de forma digital, através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL - Very High Speed Integrated Circuit Hardware Description Language) e implementado em um dispositivo FPGA (Field Programmable Gate Array) Spartan 3. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos compensadores, onde será aplicada uma metodologia de projeto capaz de projetar estes compensadores utilizando os diagramas de Bode, de módulo e de fase, e ainda contemplar as influencias dos dispositivos A/D, D/A e do processador digital de sinais. Isto eliminará os erros presentes nos projetos via aproximação e permitirá a diminuição das taxas de aquisição necessárias. O projeto é simulado e validado através da plataforma MatLab/Simulink, onde são apresentados resultados para o regime permanente e para transitórios de carga e da tensão de alimentação. Além disso, o controle do conversor através da linguagem VHDL, usando o modelo comportamental num estilo de projeto topdown, é apresentado e também validado através de simulação. Ademais, um sucinto estudo dos reatores eletrônicos convencionais é apresentado, com o intuito de sevir como base para o desenvolvimento de um filtro capaz de barrar as componentes em ca da corrente que circula entre o capacitor de saída... (Resumo completo clicar acesso eletrônico abaixo) / Abstract: This work presents the analysis, development and implementation of a single-phase power factor correction (PFC) pre-regulator rectifier, based on boost circuit, to act as a power supply for 1.200 watts multi-lamp fluorescent systems. The converter's digital control will be implemented using the average current mode control, based on VHDL language (VHSIC HDL - Very High Speed Integrated Circuit Hardware Description Language) and using a FPGA (Field Programmable Gate Array) device. In this work, the mathematical analyses of the converter's model are developed in order to obtain the proper transfer functions to design voltage and current digital compensators. The methodology applied at the digital design is capable to deal with the Bode diagrams and incorporate the analog to digital converter, the digital to analog converter and the digital signal processor, eliminating the uncertainties involving approximation methodologies and minimizing the necessity of high level of acquisition rates. This project is evaluated through MatLab/Simulink, showing results for steady-state operation and dynamics in order to analyze the converter's response. Moreover, the converter's digital control is based on VHDL language, using the behavioral modeling in a top-down project style, which is presented and validated through simulation results. In addition, the behavior of the conventional electronic ballasts are presented in order to help in the development of a filter, capable to impede the circulation of the AC components of the ballast current throught the feeding link, guaranteeing the continuous current conduction, among the boost capacitor and the electronic ballasts. Finally, this work presents the laboratorial development of this PFC with digital control, where the prototype was evaluated through experimental results. / Orientador: Carlos Alberto Canesin / Coorientador: Fabio Toshiaki Wakabayashi / Banca: Claudio Kitano / Banca: Arnaldo José Perin / Mestre

Made available in DSpace on 2014-06-11T19:22:36Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-05-14Bitstream added on 2014-06-13T18:08:35Z : No. of bitstreams: 1 brito_mag_me_ilha.pdf: 1676298 bytes, checksum: 52c7782c077571e9aa0d479e44fb3971 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Este trabalho trata da análise, desenvolvimento e implementação de um estágio Pré- Regulador Retificador Boost de alto fator de potência, para servir como fonte de alimentação para sistemas de iluminação fluorescente multi-lâmpadas, com potência de até 1.200 watts e com índices de qualidade tanto para a fonte de alimentação em corrente alternada quanto para o sistema de iluminação. Este conversor será controlado de forma digital, através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado em um dispositivo FPGA (Field Programmable Gate Array) Spartan 3. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos compensadores, onde será aplicada uma metodologia de projeto capaz de projetar estes compensadores utilizando os diagramas de Bode, de módulo e de fase, e ainda contemplar as influencias dos dispositivos A/D, D/A e do processador digital de sinais. Isto eliminará os erros presentes nos projetos via aproximação e permitirá a diminuição das taxas de aquisição necessárias. O projeto é simulado e validado através da plataforma MatLab/Simulink, onde são apresentados resultados para o regime permanente e para transitórios de carga e da tensão de alimentação. Além disso, o controle do conversor através da linguagem VHDL, usando o modelo comportamental num estilo de projeto topdown, é apresentado e também validado através de simulação. Ademais, um sucinto estudo dos reatores eletrônicos convencionais é apresentado, com o intuito de sevir como base para o desenvolvimento de um filtro capaz de barrar as componentes em ca da corrente que circula entre o capacitor de saída... / This work presents the analysis, development and implementation of a single-phase power factor correction (PFC) pre-regulator rectifier, based on boost circuit, to act as a power supply for 1.200 watts multi-lamp fluorescent systems. The converter’s digital control will be implemented using the average current mode control, based on VHDL language (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) and using a FPGA (Field Programmable Gate Array) device. In this work, the mathematical analyses of the converter´s model are developed in order to obtain the proper transfer functions to design voltage and current digital compensators. The methodology applied at the digital design is capable to deal with the Bode diagrams and incorporate the analog to digital converter, the digital to analog converter and the digital signal processor, eliminating the uncertainties involving approximation methodologies and minimizing the necessity of high level of acquisition rates. This project is evaluated through MatLab/Simulink, showing results for steady-state operation and dynamics in order to analyze the converter’s response. Moreover, the converter’s digital control is based on VHDL language, using the behavioral modeling in a top-down project style, which is presented and validated through simulation results. In addition, the behavior of the conventional electronic ballasts are presented in order to help in the development of a filter, capable to impede the circulation of the AC components of the ballast current throught the feeding link, guaranteeing the continuous current conduction, among the boost capacitor and the electronic ballasts. Finally, this work presents the laboratorial development of this PFC with digital control, where the prototype was evaluated through experimental results.

The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.

V systému s kódy zbytkových tříd je základem skupina navzájem nezávislých bází. Číslo ve formátu integer je reprezentováno kratšími čísly integer, které získáme jako zbytky všech bází, a aritmetické operace probíhají samostatně na každé bázi. Při aritmetických operacích nedochází k přenosu do vyšších řádů při sčítání, odečítání a násobení, které obvykle potřebují více strojového času. Srovnávání, dělení a operace se zlomky jsou komplikované a chybí efektivní algoritmy. Kódy zbytkových tříd se proto nepoužívají k numerickým výpočtům, ale jsou velmi užitečné pro digitální zpracování signálu. Disertační práce se týká návrhu, simulace a mikropočítačové implementace funkčních bloků pro digitální zpracování signálu. Funkční bloky, které byly studovány jsou nově navržené konvertory z binarní do reziduální reprezentace a naopak, reziduální sčítačka a násobička. Nově byly také navržené obslužné algoritmy.

The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.