NDLTD Global ETD Search
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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 1 to 10 of 681 (0.02 seconds)
1

ILP-basierte Mikroarchitektur-Synthese mit komplexen Bausteinbibliotheken : Wege zu kleineren und schnelleren Schaltungen unter Einsatz algebraischer Optimierungen /

Landwehr, Birger. January 1998 (has links) (PDF)
Univ., Diss.--Dortmund, 1998. / Literaturverz. S. 183 - 196.
VLSI
2

Layout and structure aware synthesis of integrated circuits

Kutzschebauch, Thomas. January 1900 (has links) (PDF)
Kaiserslautern, Univ., Diss., 2003. / Computerdatei im Fernzugriff.
VLSI
3

Eine graphische Arbeitsumgebung für den parametrisierten Entwurf integrierter Schaltkreise

Burch, Thomas. January 1900 (has links) (PDF)
Saarbrücken, Univ., Diss., 1995. / Erscheinungsjahr an der Haupttitelstelle: 1994. Computerdatei im Fernzugriff.
VLSI
4

Automatisierter Systementwurf in der digitalen Signalverarbeitung auf der Basis von Schaltungsstrukturen der Restklassenarithmetik

Henkelmann, Heiko. January 2004 (has links) (PDF)
Bremen, Univ., Diss., 2004. / Computerdatei im Fernzugriff.
VLSI
5

Entwurfsmethoden für verlustarme integrierte Schaltungen

Schimpfle, Christian Vinzenz. January 2000 (has links)
München, Techn. Universiẗat, Diss., 2000. / Elektronische Ressource verfügbar im PS- und PDF-Format.
VLSI
6

Contributions to low energy consumption in digital circuits

Bühler, Markus. January 2000 (has links) (PDF)
Stuttgart, University, Diss., 2000.
VLSI
7

Laserumschalterstruktur in CMOS-Technologie

Mende, Ole. January 2003 (has links) (PDF)
Hannover, Universiẗat, Diss., 2003.
VLSI
8

Placement for structured ASICs

Kumar, Anurag, 1983- 25 August 2010 (has links)
Structured ASICs provide an exciting middle-ground between ASIC and FPGA design styles because they provide trade-off between the high per- formance of ASIC design and low costs of FPGA design. To fully utilize the benefits of structured ASIC, placement stage must be aware of the modularity of the structured ASIC architecture. This work describes a novel solution to placement of structured ASICs. Integer linear programming formulation is proposed for satisfying the constraints associated with structured ASIC clock architecture. Regularity of the platform is exploited during legalization and wirelength recovery stages to speed-up the detailed placement stage. Our methods show overall wirelength reduction up to 33% and up to 3X speedup compared to other placers. / text
Placement, Vlsi
9

Performance and energy efficient building blocks for network-on-chip architectures /

Vangal, Sriram R., January 2006 (has links)
Licentiatavhandling Linköping : Linköpings universitet, 2006.
VLSI. Chips
10

Chip Assembly mit topologischer Kompaktiertung /

Pape, Markus. January 1995 (has links)
Universiẗat-Gesamthochsch., Diss.--Paderborn, 1995.
Entwurfsautomation. VLSI.

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