No description available.

As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires.

Universiẗat, Diss.--Paderborn, 1994.

Universiẗat, Diss., 1995--Saarbrücken. / Erscheinungsjahr an der Haupttitelstelle: 1994.

Universiẗat, Diss., 2004--Bremen.

Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. This second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.

No description available.

No description available.

The growing demand for high-performance computing platforms has pushed the computing community to invent new architectures for processors. Recently, researchers have begun to solve the problem by the implementation of Field-Programming Gate Arrays (FPGAs). FPGAs make it possible to implement different applications on the same hardware. Unfortunately, FPGAs suffer from low bandwidth, density, and throughout. To gain the flexibility of FPGAs and to gain more computational capacity than conventional processors have, Wormhole run-time reconfigurable (RTR) techniques has been developed to address some high performance digital signal processing (DSP) problems. Multiplication is one of the basic functions used in digital signal processing. Most high-performance DSP systems rely on hardware multiplication to achieve high data throughput. To meet the processing needs of DSP, a multiplier was embedded into a prototype wormhole RTR device called Colt, but because each design has its own speed and size requirements, rarely can a designer take an already existing multiplier module and use it in Colt. Therefore redesigning multipliers is necessary for meeting the system specifications of Colt. This thesis explores the design of the multiplier from architecture level to circuit level. / Master of Science

Until now, the performance improvement of computing machines was a mostly a result of shrinking transistor geometries and increasing clock speeds. With the advent of signal processing applications that have stringent performance requirements from processing hardware, the field of configurable computing has received a lot of attention. Efforts are being made to improve computation bandwidth by architectural innovations. Among these, the wormhole runtime reconfigurable architecture introduces the concept of stream processing. It enables dynamic reconfiguration of hardware with little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, second in the generation of Wormhole runtime reconfigurable processors, demonstrates the efficacy of wormhole runtime reconfiguration. The work presented here deals with the VLSI implementation of Stallion and discusses the full-custom physical design flow adopted for Stallion. Also, the tools and techniques to customize this flow are detailed. The Stallion design methodology offers a possible solution that can be pursued for executing similar efforts in future. / Master of Science