abstract: Multidimensional (MD) discrete Fourier transform (DFT) is a key kernel algorithm in many signal processing applications, such as radar imaging and medical imaging. Traditionally, a two-dimensional (2-D) DFT is computed using Row-Column (RC) decomposition, where one-dimensional (1-D) DFTs are computed along the rows followed by 1-D DFTs along the columns. However, architectures based on RC decomposition are not efficient for large input size data which have to be stored in external memories based Synchronous Dynamic RAM (SDRAM). In this dissertation, first an efficient architecture to implement 2-D DFT for large-sized input data is proposed. This architecture achieves very high throughput by exploiting the inherent parallelism due to a novel 2-D decomposition and by utilizing the row-wise burst access pattern of the SDRAM external memory. In addition, an automatic IP generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2048x2048 input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations. While the proposed 2-D DFT IP can achieve high performance, its output is bit-reversed. For systems where the output is required to be in natural order, use of this DFT IP would result in timing overhead. To solve this problem, a new bandwidth-efficient MD DFT IP that is transpose-free and produces outputs in natural order is proposed. It is based on a novel decomposition algorithm that takes into account the output order, FPGA resources, and the characteristics of off-chip memory access. An IP generator is designed and integrated into an in-house FPGA development platform, AlgoFLEX, for easy verification and fast integration. The corresponding 2-D and 3-D DFT architectures are ported onto the BEE3 board and their performance measured and analyzed. The results shows that the architecture can maintain the maximum memory bandwidth throughout the whole procedure while avoiding matrix transpose operations used in most other MD DFT implementations. The proposed architecture has also been ported onto the Xilinx ML605 board. When clocked at 100 MHz, 2048x2048 images with complex single-precision can be processed in less than 27 ms. Finally, transpose-free imaging flows for range-Doppler algorithm (RDA) and chirp-scaling algorithm (CSA) in SAR imaging are proposed. The corresponding implementations take advantage of the memory access patterns designed for the MD DFT IP and have superior timing performance. The RDA and CSA flows are mapped onto a unified architecture which is implemented on an FPGA platform. When clocked at 100MHz, the RDA and CSA computations with data size 4096x4096 can be completed in 323ms and 162ms, respectively. This implementation outperforms existing SAR image accelerators based on FPGA and GPU. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

Made available in DSpace on 2014-06-12T15:58:17Z (GMT). No. of bitstreams: 2 arquivo3360_1.pdf: 1861373 bytes, checksum: da4095d44ee2bf2199c241b47e6516e9 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010 / Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às tendências de mercado atuais, dispositivos portáteis, alimentados à bateria, estão sendo cada vez mais procurados, de modo que uma demanda de produtos que tenham uma maior capacidade de prolongar a vida útil das baterias vem crescendo. Recentemente, a redução do tamanho do transistor propiciou uma mudança no comportamento das componentes de energia em transistores CMOS. A componente estática que antigamente era praticamente desprezada tem aumentado exponencialmente com alterações não proporcionais, tais como diminuição do canal e redução de tensão de alimentação dos circuitos. Atualmente, esta componente estática representa uma fração significante da potência total consumida em circuitos com tecnologias de fabricação abaixo de 90 nm, podendo passar de 50% da potência total. Este consumo torna-se cada vez mais expressivo à medida que as tensões de alimentação dos circuitos são reduzidas, devido à necessidade de se minimizar a tensão de threshold para manter o desempenho dos circuitos. O algoritmo desenvolvido para a redução de potência estática em circuitos integrados digitais pode ser inserido no fluxo de desenvolvimento, sem causar penalidades ao mesmo. Na abordagem proposta, baseada na técnica Dual-Threshold, parte das células do circuito é substituída por células com tensão de threshold mais alta sem que haja inserção de violações de tempo no circuito. A troca de cada célula é definida a partir de estimativas do comportamento do circuito caso a célula seja trocada, antes que ela seja de fato substituída. Ao contrário de abordagens baseadas em caminhos, a característica de não haver trocas a cada análise das células do circuito, permite uma redução significativa no tempo de execução do algoritmo. Os resultados obtidos, que apresentaram uma redução de potência estática de até 39%, resultaram da execução do algoritmo utilizando circuitos do benchmark ISCAS85

Made available in DSpace on 2014-06-12T15:58:18Z (GMT). No. of bitstreams: 2 arquivo3452_1.pdf: 3452194 bytes, checksum: f140ad60d48eddac72b254cec44bfe46 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2011 / O advento das novas tecnologias Very Large Scale Integration (VLSI) e o crescimento da demanda por produtos eletrônicos no mundo estão trazendo um aumento explosivo na complexidade dos circuitos eletrônicos. A contrario sensu, o tempo de mercado (time-tomarket) de um produto eletrônico, e o tempo de projeto necessário para produção e venda de um sistema estão ficando cada vez menores. Para que o circuito integrado chegue ao mercado com o funcionamento esperado é necessário realizar testes. Parte desses testes é chamada de verificação funcional e é a parte do projeto que requer mais tempo de desenvolvimento. Buscam-se sempre novos métodos que permitam que a verificação funcional seja realizada de forma ágil, fácil e que proveja uma maior reusabilidade e diminuição da complexidade na construção do ambiente de simulação, sem interferir negativamente na qualidade do processo de verificação e do produto. Dessa forma, o uso de uma metodologia de verificação funcional eficiente e de ferramentas que auxiliem o engenheiro de verificação funcional é de grande valia. A metodologia OVM_tpi permite o desenvolvimento de todo o fluxo de construção de um ambiente de verificação, independente da escolha feita pela equipe desenvolvedora, de forma que o ambiente de simulação seja gerado antes da implementação do circuito a ser verificado (Design Under Verification - DUV). Além disso, ataca os principais desafios do processo de verificação funcional, tempo e custo de desenvolvimento, contribuindo para uma diminuição da complexidade, reusabilidade, comunicação entre o ambiente com uma interface bem definida e diminuição no tempo de desenvolvimento de um testbench através do uso de templates que criam de forma semiautomática partes do ambiente de verificação. OVM_tpi teve como principal base a metodologia Open Verification Methodology (OVM), utilizando sua biblioteca para a construção do testbench e o paradigma de linguagem orientação objeto suportado por SystemVerilog, linguagem criada especialmente para verificação funcional e design. Sua validação foi através de estudos de casos que demonstraram a eficácia do seu uso, tanto para circuitos unidirecionais, quanto para bidirecionais

Application of neural prostheses in today's medicine successfully helps patients to increase their activities of daily life and participate in social activities again. These implantable microsystems provide an interface to the nervous system, giving cellular resolution to physiological processes unattainable today with non-invasive methods. The latest developments in genetic engineering, nanotechnologies and materials science have paved the way for these complex systems to interface the human nervous system. The ideal system for neural signal recording would be a fully implantable device which is capable of amplifying the neural signals and transmitting them to the outside world while sustaining a long-term and accurate performance, therefore different sciences from neurosciences, biology, electrical engineering and computer science have to interact and discuss the synergies to develop a practical system which can be used in daily medicine practice. This work investigates the main building blocks necessary to improve the quality of acquired signal from the micro-electronics and MEMS perspectives. While all of these components will be ultimately embedded in a fully implantable recording probe, each of them addresses and deals with a specific obstacle in the neural signal recording path. Specifically we present a low-voltage low-noise low-power CMOS amplifier particularly designed for neural recording applications. This is done by surveying a number of designs and evaluating each design against the requirements for a neural recording system such as power dissipation and noise, and then choosing the most suitable topology for design and implementation of a fully implantable system. In addition a surface modification method is investigated to improve the sacrificial properties and biocompatibility of probe in order to extend the implant life and enhance the signal quality. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Information in the form of online multimedia, bank accounts, or password usage for diverse applications needs some form of security. the core feature of many security systems is the generation of true random or pseudorandom numbers. Hence reliable generators of such numbers are indispensable. the fundamental hurdle is that digital computers cannot generate truly random numbers because the states and transitions of digital systems are well understood and predictable. Nothing in a digital computer happens truly randomly. Digital computers are sequential machines that perform a current state and move to the next state in a deterministic fashion. to generate any secure hash or encrypted word a random number is needed. But since computers are not random, random sequences are commonly used. Random sequences are algorithms that generate a pattern of values that appear to be random but after some time start repeating. This thesis implements a digital random number generator using MATLAB, FGPA prototyping, and custom silicon design. This random number generator is able to use a truly random CMOS source to generate the random number. Statistical benchmarks are used to test the results and to show that the design works. Thus the proposed random number generator will be useful for online encryption and security.

Information in the form of online multimedia, bank accounts, or password usage for diverse applications needs some form of security. the core feature of many security systems is the generation of true random or pseudorandom numbers. Hence reliable generators of such numbers are indispensable. the fundamental hurdle is that digital computers cannot generate truly random numbers because the states and transitions of digital systems are well understood and predictable. Nothing in a digital computer happens truly randomly. Digital computers are sequential machines that perform a current state and move to the next state in a deterministic fashion. to generate any secure hash or encrypted word a random number is needed. But since computers are not random, random sequences are commonly used. Random sequences are algorithms that generate a pattern of values that appear to be random but after some time start repeating. This thesis implements a digital random number generator using MATLAB, FGPA prototyping, and custom silicon design. This random number generator is able to use a truly random CMOS source to generate the random number. Statistical benchmarks are used to test the results and to show that the design works. Thus the proposed random number generator will be useful for online encryption and security.

Binary multiplier has been a staple in the digital circuit design. It is used in microprocessor design, DSP applications etc. Here, we discuss the design of a novel multiplier that employs a modified shift and add logic to multiply two n-bit unsigned binary numbers. In our work, we changed the shift and add algorithm. We used a barrel shifter and a multiplexer to generate the partial products. We also found out a way to reduce the number of partial products so that we would have fewer numbers to add after we generated all of them. An array of Carry Save Adders (CSA) is used to add the partial products. With all our arrangements and setups, we aim to reduce delays and make the design as efficient as possible. As examples, we have shown it to multiply two 16-bit numbers, however, the design can easily be either scaled up or down according to the environment the multiplier is being used.

Static Random Access Memory (SRAM) is a critical component in mobile video processing systems. Because of the large video data size, the memory is frequently accessed, which dominates the power consumption and limits battery life. In energy-efficient SRAM design, a substantial amount of research is presented to discuss the mechanisms of approximate storage, but the content and environment adaptations were never a part of the consideration in memory design. This dissertation focuses on optimization methods for the SRAM system, specifically addressing three areas of Intelligent Energy-Efficient Storage system design. First, the SRAM stability is discussed. The relationships among supply voltage, SRAM transistor sizes, and SRAM failure rate are derived in this section. The result of this study is applied to all of the later work. Second, intelligent voltage scaling techniques are detailed. This method utilizes the conventional voltage scaling technique by integrating self-correction and sizing techniques. Third, intelligent bit-truncation techniques are developed. Viewing environment and video content characteristics are considered in the memory design. The performance of all designed SRAMs are compared to published literature and are proven to have improvement.

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