Packet switches are used in the Internet to forward information between a sender and receiver and are the critical bottleneck in the Internet. Without faster packet switch designs, the Internet cannot continue to scale-up to higher data rates. Packet switches must be able to achieve high throughput and low delay. In addition, they must be stable for all traffic loads, must efficiently support variable length packets, and must be scalable to higher link data rates and greater numbers of ports. This dissertation investigates a new combined input and crossbar queued (CICQ) switch architecture. Some unbalanced traffic loads result in instability for input queued (IQ) and CICQ switches. This instability region was modeled, and the cause of the instability was found to be a lack of work conservation at one port. A new burst stabilization protocol was investigated that was shown to stabilize both IQ and CICQ switches. As an added benefit, this new protocol did not require a costly internal switch speed-up. Switching variable length packets in IQ switches requires the segmentation of packets into cells. The process also requires an internal switch speed-up which can be costly. A new method of cell-merging in IQ switches reduced this speed-up. To improve fairness for CICQ switches, a block and transfer method was proposed and evaluated. Implementation feasibility of the CICQ switch was also investigated via a field programmable gate array (FPGA) implementation of key components. Two new designs for round robin arbiters were developed and evaluated. The first of these, a proposed priority-encoder-based round robin arbiter that uses feedback masking, has a lower delay than any known design for an FPGA implementation. The second, an overlapped round robin arbiter design that fully overlaps round robin polling and scheduling, was proposed and shown to be scalable, work conserving, and fair. To allow for multi-cabinet implementation and minimization of the size of the cross point buffers, a distributed input port queue scheduler was investigated. This new scheduler minimizes the amount of buffering needed within the crossbar. The two primary contributions of this dissertation are 1) a complete understanding of the performance characteristics of the CICQ switch, and 2) new methods for improving the performance, stability,and scalability of the CICQ switch. This work has shown that the CICQ switch can be the switch architecture of the future.

The objective of the research is to design an electro-optic control for the Active Vertical Coupler-based Optical Cross-point Switch (OXS). The electronic control should be implemented on Printed Circuit Board (PCB) and therefore the design will include the PCB design as well. The aim of the electronic control board is to process the headers of the packets prior to entering the OXS to be switched and from the information in the headers, determine the state that the OXS should be configured in. It should then configure the optical cross-point accordingly. The electronic control board should show flexibility in the sense that it can handle different types of traffic and resolve possible contention that may occur. The research seeks to understand the problems associated with Photonic Packet Switching (PPS) networks. Two of the main problems identified in a PPS network are contention resolution and the lack of variable delays for storing optical packets. The OXS was analyzed and found to meet the requirements for future ultra-high speed PPS network technology with its high extinction ratio, wide optical bandwidth, ultra-fast switching speed and low crosstalk levels. Photonic packets were generated with 4-bit, 8-bit or 16-bit headers at a bit rate of 155 Mbit/s followed by a PRBS (Pseudo Random Bit Sequence) payload at 10 Gbit/s. Different scenarios were created with these types of packets and the electro-optic control and OXS were subjected to these scenarios with the aim of testing the flexibility of the electro-optic control to control the OXS. These scenarios include: <ul><li>Fixed length packets arriving synchronously at one input of the OXS. Some packets are destined for output 1, some are destined for output 2 and some are destined for output 3, therefore realizing a 1-to-3 optical switch.</li> <li>Eight variable length packets arriving synchronously at the OXS at one input, all of them destined for one output. The electro-optic control should open the switch cell for the correct amount of time.</li> <li>Three variable length packets arriving synchronously and asynchronously at one input of the OXS. Some packets are destined for output 1 while other packets are destined for output 2. The electro-optic control should open the correct switch cell for the correct amount of time.</li> <li>Two fixed length packets arriving at the OXS synchronously on different input ports at the same time, both destined for the same output port. The electro-optic control should detect the contention and switch the packets in such a way as to resolve the contention.</li> The electro-optic control and OXS managed to switch all these types of data traffic (scenarios) successfully and resolve the contention with an optical delay buffer. The success of the results was measured in two ways. Firstly it was deemed successful if the expected output sequence was measured at the corresponding output ports. Secondly it was successful if the degradation in quality of the packet was not drastic, meaning the output packets should have an BER (Bit Error Rate) of less than 10-9. The quality of the packets was measured in the form of eye diagrams before and after the switching and then compared. The research resulted in the design and implementation of a flexible electro-optic control for the OXS. The problem of contention was resolved for fixed length synchronous packets and a proposal is discussed to store packets for variable lengths of time by using the OXS. This electro-optic control has the potential to control the OXS for traffic with higher complexities and make the OXS compatible with future developments. / Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2008. / Electrical, Electronic and Computer Engineering / MEng / unrestricted