Zugl.: Erlangen, Nürnberg, Univ., Diss., 2007

Zugl.: Erlangen-Nürnberg, Universiẗat, Diss., 2007.

The purpose of this thesis is to develop the architecture to use the Car2X for observation the local traffic sign and displays it on the OpenStreetMap to provide more information of the road side to the driver. The proposed architecture of this thesis is to convert the traffic sign into the barcode and to be scanned by the barcode scanner and then wirelessly transfers the data to the web server to store the data and displays the traffic sign on the OpenStreetMap in the web browser. It uses two Raspberry Pi boards with CAN-Bus shields for transmitting the data on the CAN-Bus system in the car, a barcode scanner to scan the barcode, a GPS module to get its location, and a WiFi dongle to wirelessly send the data. The thesis also includes the camera to detect the traffic light using OpenCV and sends the GO or STOP command to the car. The results provide the OpenStreetMap with the traffic sign which helps the driver to realize the traffic sign on the road of the desired destination. However, the accuracy of GPS is not satisfied as well as the distance of the barcode scanning, therefore, this thesis suggests that includes the gps position in the barcode and uses the camera to detect the barcode for the improvement in the future.

Thesis--Universitat-Gesamthochschule Paderborn.

The purpose of this thesis is to develop the architecture to use the Car2X for observation the local traffic sign and displays it on the OpenStreetMap to provide more information of the road side to the driver. The proposed architecture of this thesis is to convert the traffic sign into the barcode and to be scanned by the barcode scanner and then wirelessly transfers the data to the web server to store the data and displays the traffic sign on the OpenStreetMap in the web browser. It uses two Raspberry Pi boards with CAN-Bus shields for transmitting the data on the CAN-Bus system in the car, a barcode scanner to scan the barcode, a GPS module to get its location, and a WiFi dongle to wirelessly send the data. The thesis also includes the camera to detect the traffic light using OpenCV and sends the GO or STOP command to the car. The results provide the OpenStreetMap with the traffic sign which helps the driver to realize the traffic sign on the road of the desired destination. However, the accuracy of GPS is not satisfied as well as the distance of the barcode scanning, therefore, this thesis suggests that includes the gps position in the barcode and uses the camera to detect the barcode for the improvement in the future.

This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the proposed system. The software system was designed and developed using C++ and OpenCV library on general purpose CPU. The prototype is used to explore and investigate potential segmentation and detection algorithms that might be feasible to design and implement in hardware accelerated environments. These algorithms includes RGB colour conversion, colour segmentation through thresholding, noise reduction through median filter, morphological operations through erosion and dilation, and sign detection through template matching. The second phase, a hardware-based design of the system was developed using the same algorithms used in the software design. The hardware design is composed of 20 image processing components each designed to xxx fully parallelized and pipelined xxx. The hardware implementation was developed using VHDL as the hardware description language targeting a Xilinix Virtex-6 FPGA XC6VLX240T device. The development environment is Xilinx ISE®Design Suite version 14.3. A set of 20 640x480 test images was used as the test data for the verification and testing of this work. The images was captured by a smart-phone camera in various weather and lightning conditions. The software implementation delivered speed limit detection results with a success rate of 75%. The hardware implementation was only simulated using Xilinx ISE Simulator (ISim) with a overall system latency of 12964 clock cycles. According to the Place and Route report the maximum operation frequency for the proposed hardware design is 71,2 MHz. The design only utilized 2% of the slice registers, 4% of the slice Look up Tables (LUT), and 11% of the block memory. This thesis project concludes the work based on the provided software and hardware implementation and performance analysis results. Also the conclusions chapter provides recommendations and future work for possible extension of the project.

This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the proposed system. The software system was designed and developed using C++ and OpenCV library on general purpose CPU. The prototype is used to explore and investigate potential segmentation and detection algorithms that might be feasible to design and implement in hardware accelerated environments. These algorithms includes RGB colour conversion, colour segmentation through thresholding, noise reduction through median filter, morphological operations through erosion and dilation, and sign detection through template matching. The second phase, a hardware-based design of the system was developed using the same algorithms used in the software design. The hardware design is composed of 20 image processing components each designed to xxx fully parallelized and pipelined xxx. The hardware implementation was developed using VHDL as the hardware description language targeting a Xilinix Virtex-6 FPGA XC6VLX240T device. The development environment is Xilinx ISE®Design Suite version 14.3. A set of 20 640x480 test images was used as the test data for the verification and testing of this work. The images was captured by a smart-phone camera in various weather and lightning conditions. The software implementation delivered speed limit detection results with a success rate of 75%. The hardware implementation was only simulated using Xilinx ISE Simulator (ISim) with a overall system latency of 12964 clock cycles. According to the Place and Route report the maximum operation frequency for the proposed hardware design is 71,2 MHz. The design only utilized 2% of the slice registers, 4% of the slice Look up Tables (LUT), and 11% of the block memory. This thesis project concludes the work based on the provided software and hardware implementation and performance analysis results. Also the conclusions chapter provides recommendations and future work for possible extension of the project.

The thesis with the title “Designing and simulating a Car2X communication system using the example of an intelligent traffic sign” has been done in Chemnitz University of Technology in the faculty of Computer Science. The purpose of this thesis is to define a layered architecture for Infrastructure to Vehicle (I2V) communication and the implementation of a sample intelligent traffic sign (variable speed limit) application for a Car2X communication system. The layered architecture of this thesis is defined based on three related projects. The application is implemented using the defined layered architecture. Considering the availability of hardware, the implementation is done using the network simulator OMNET++. To check the feasibility of the application three scenarios are created and integrated with the application. The evaluation is done based on the result log files of the simulation which show that the achieved results conform with the expected results, except some minor limitations.

The thesis with the title “Designing and simulating a Car2X communication system using the example of an intelligent traffic sign” has been done in Chemnitz University of Technology in the faculty of Computer Science. The purpose of this thesis is to define a layered architecture for Infrastructure to Vehicle (I2V) communication and the implementation of a sample intelligent traffic sign (variable speed limit) application for a Car2X communication system. The layered architecture of this thesis is defined based on three related projects. The application is implemented using the defined layered architecture. Considering the availability of hardware, the implementation is done using the network simulator OMNET++. To check the feasibility of the application three scenarios are created and integrated with the application. The evaluation is done based on the result log files of the simulation which show that the achieved results conform with the expected results, except some minor limitations.