Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data. A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4£c-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost. The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power. Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

The first topic of this thesis proposes a digital video decoder for NTSC. The new fully digital design employs a DDFS (digital direct frequency synthesizer) and an adaptive digital PLL to track and lock the demodulation carrier. The complexity of the digital video decoder, hence, is drastically reduced. The overall cost of the proposed design is 6.0 mm2 (39K gates). The maximum power dissipation is 86 mW at the hightest clock rate which is 21.48 MHz. The second topic is to carry out a codec (encoder-decoder) design for interfacing variable-length and fixed-length data compression. The poor memory efficiency caused by the variable-length words converting into a fixed-length packet such that the compression can be hardwaredly and parallelly processing is significantly improved. The proposed codec is to encode more symbols in the redundant bits of the padding bits of the fixed-length packets. This novel encoding scheme relaxes the intrinsic poor bit rate of the traditional fixed-length data compression.

The first topic of the thesis presents an NTSC digital video decoder which is designed by using two lines delay comb filter to decode the luminance signal (Y) and the chrominance signal (C). The coefficients of the low pass filter are tuned properly to reduce the gate count without losing any original performance of the chroma demodulator. The second topic of the thesis is to propose a method and a circuitry to resolve the out-of-phase problem between the color burst and the sub-carrier in NTSC TV receivers. The feature of the method is that a delay means is inserted which leads to the synchronization of the color burst and the sub-carrier such that the following color demodulator is able to extract right color signals. Besides, the locking of the two signals will be fastened without any extra large circuit cost.

Tato práce představuje návrh na vytvoření dekodéru pro video zaznamenané pomocí softwaru Magic Lantern, který může být nainstalován na Canon 5D. Toto video je význačné pro svoji velikost 14-bitů v raw formátu a proto může produkovat velmi kvalitní výstup. Práce má za cíl rozdělit video do jednotlivých snímků, ve vhodném formátu, který umí pracovat také s formáty obrazů s vysokým dynamickým rozsahem.

As redes-em-chip (NoCs) surgiram como uma alternativa aos atuais problemas de interconexão decorrentes da redução da escala de tecnologia de fabricação de circuitos integrados. O desenvolvimento de transistores com nanômetros de largura tem permitido a inserção de sistemas altamente complexos em uma única pastilha de silício. Dessa forma, os SoCs (Systems-on-Chip) passaram a constituir inúmeros elementos de processamentos (EPs) e as NoCs têm se apresentado como uma opção eficiente no provimento da interconexão dos mesmos, permitindo maior escalabilidade e paralelismo ao sistema. No entanto, esta conexão não é realizada de forma direta. Todo sistema conectado por uma NoC necessita de interfaces de rede (NIs) para intermediar a conexão dos elementos de processamento aos roteadores da rede. O objetivo desse trabalho é apresentar soluções arquiteturais de interfaces de rede para NoCs que atendam diferentes aplicações de forma genérica. Neste trabalho foram desenvolvidas interfaces de redes reutilizáveis e parametrizáveis, e para atender a estas características, as interfaces de rede possibilitam a configuração de diversos parâmetros arquiteturais, como largura da palavra de dados dos EPs, profundidade das FIFOs das interfaces, profundidade das FIFOs da NoC e largura de dados da rede, possibilitando prover a interconexão de qualquer aplicação com um mínimo de reprojeto. As interfaces de rede, juntamente com a NoC, são responsáveis pelo desempenho da comunicação da aplicação e, para isso, o projeto de uma NI deve ser capaz de atender aos requisitos do sistema, por isso, a importância de se obter um projeto de NIs flexível. Para validar as arquiteturas das NIs desenvolvidas, os módulos do decodificador de vídeo no contexto do padrão H.264 foram conectados à NoC através das interfaces projetadas. A partir dessa implementação, puderam-se levantar diversas necessidades que devem ser atendidas pelas NIs. Por fim, foram analisados os resultados de síntese das NIs para diferentes configurações. Também foram verificados os resultados de síntese e desempenho do decodificador de vídeo H.264 conectado pelas NIs à NoC. Com relação aos resultados de síntese em FPGA, a implementação do decodificador de vídeo com NoC e NIs não apresentou um grande aumento em área quando comparada a implementação com conexão ponto-a-ponto. Além disso, para diferentes configurações das NIs, a NoC pode ser utilizada atendendo aos requisitos de desempenho exigidos pela aplicação, sem a necessidade de operar na sua máxima taxa de operação para a resolução QCIF. / Networks-on-Chip (NoCs) have emerged as an alternative to the current interconnection problems arising from the scaling technology for manufacturing integrated circuits. The development of transistors with nanometer-wide has enabled the integration of highly complex systems on a single silicon wafer. Thus, SoCs (Systemson- Chip) have integrated numerous processing elements (EPs) and NoCs have been presented as an effective option in providing the interconnection of these elements, allowing scalability and parallelism to the system. However, this connection is not done directly. Every system connected by NoC needs network interfaces to intermediate the connection of processing elements to network routers. The goal of this thesis is to present architectural solutions for network interfaces for applications in general. In this work we developed a generic, reusable and configurable network interface. The proposed network interface enables the configuration of several architectural parameters, such as data width of the packets, FIFOs depth of the interfaces, FIFO depth and data width of the NoC, and thus, being able to provide the interconnection of any application with a minimal redesign. Network interfaces, together with the NoC, are responsible for application performance and, therefore, the design of an NI should be able to support the system requirements. To validate the architecture of developed NI, the modules of H.264 decoder were connected to NoC through designed interface. From this implementation, one could raise several needs that must be supported by the NIs. Finally, we analyzed the results of synthesis of the NIs for different configurations. It was also analyzed the results of synthesis and performance of H.264 video decoder connected by NIs to NoC. According to results for FPGA synthesis, the implementation of video decoder with NoC and NIs did not show a large increase in area when compared with the implementation of peer-to-peer. Moreover, for different configurations, the NoC can be used according to time requisitions required by the application, without the need to operate at its maximum operation frequency for QCIF resolution.

As redes-em-chip (NoCs) surgiram como uma alternativa aos atuais problemas de interconexão decorrentes da redução da escala de tecnologia de fabricação de circuitos integrados. O desenvolvimento de transistores com nanômetros de largura tem permitido a inserção de sistemas altamente complexos em uma única pastilha de silício. Dessa forma, os SoCs (Systems-on-Chip) passaram a constituir inúmeros elementos de processamentos (EPs) e as NoCs têm se apresentado como uma opção eficiente no provimento da interconexão dos mesmos, permitindo maior escalabilidade e paralelismo ao sistema. No entanto, esta conexão não é realizada de forma direta. Todo sistema conectado por uma NoC necessita de interfaces de rede (NIs) para intermediar a conexão dos elementos de processamento aos roteadores da rede. O objetivo desse trabalho é apresentar soluções arquiteturais de interfaces de rede para NoCs que atendam diferentes aplicações de forma genérica. Neste trabalho foram desenvolvidas interfaces de redes reutilizáveis e parametrizáveis, e para atender a estas características, as interfaces de rede possibilitam a configuração de diversos parâmetros arquiteturais, como largura da palavra de dados dos EPs, profundidade das FIFOs das interfaces, profundidade das FIFOs da NoC e largura de dados da rede, possibilitando prover a interconexão de qualquer aplicação com um mínimo de reprojeto. As interfaces de rede, juntamente com a NoC, são responsáveis pelo desempenho da comunicação da aplicação e, para isso, o projeto de uma NI deve ser capaz de atender aos requisitos do sistema, por isso, a importância de se obter um projeto de NIs flexível. Para validar as arquiteturas das NIs desenvolvidas, os módulos do decodificador de vídeo no contexto do padrão H.264 foram conectados à NoC através das interfaces projetadas. A partir dessa implementação, puderam-se levantar diversas necessidades que devem ser atendidas pelas NIs. Por fim, foram analisados os resultados de síntese das NIs para diferentes configurações. Também foram verificados os resultados de síntese e desempenho do decodificador de vídeo H.264 conectado pelas NIs à NoC. Com relação aos resultados de síntese em FPGA, a implementação do decodificador de vídeo com NoC e NIs não apresentou um grande aumento em área quando comparada a implementação com conexão ponto-a-ponto. Além disso, para diferentes configurações das NIs, a NoC pode ser utilizada atendendo aos requisitos de desempenho exigidos pela aplicação, sem a necessidade de operar na sua máxima taxa de operação para a resolução QCIF. / Networks-on-Chip (NoCs) have emerged as an alternative to the current interconnection problems arising from the scaling technology for manufacturing integrated circuits. The development of transistors with nanometer-wide has enabled the integration of highly complex systems on a single silicon wafer. Thus, SoCs (Systemson- Chip) have integrated numerous processing elements (EPs) and NoCs have been presented as an effective option in providing the interconnection of these elements, allowing scalability and parallelism to the system. However, this connection is not done directly. Every system connected by NoC needs network interfaces to intermediate the connection of processing elements to network routers. The goal of this thesis is to present architectural solutions for network interfaces for applications in general. In this work we developed a generic, reusable and configurable network interface. The proposed network interface enables the configuration of several architectural parameters, such as data width of the packets, FIFOs depth of the interfaces, FIFO depth and data width of the NoC, and thus, being able to provide the interconnection of any application with a minimal redesign. Network interfaces, together with the NoC, are responsible for application performance and, therefore, the design of an NI should be able to support the system requirements. To validate the architecture of developed NI, the modules of H.264 decoder were connected to NoC through designed interface. From this implementation, one could raise several needs that must be supported by the NIs. Finally, we analyzed the results of synthesis of the NIs for different configurations. It was also analyzed the results of synthesis and performance of H.264 video decoder connected by NIs to NoC. According to results for FPGA synthesis, the implementation of video decoder with NoC and NIs did not show a large increase in area when compared with the implementation of peer-to-peer. Moreover, for different configurations, the NoC can be used according to time requisitions required by the application, without the need to operate at its maximum operation frequency for QCIF resolution.

As redes-em-chip (NoCs) surgiram como uma alternativa aos atuais problemas de interconexão decorrentes da redução da escala de tecnologia de fabricação de circuitos integrados. O desenvolvimento de transistores com nanômetros de largura tem permitido a inserção de sistemas altamente complexos em uma única pastilha de silício. Dessa forma, os SoCs (Systems-on-Chip) passaram a constituir inúmeros elementos de processamentos (EPs) e as NoCs têm se apresentado como uma opção eficiente no provimento da interconexão dos mesmos, permitindo maior escalabilidade e paralelismo ao sistema. No entanto, esta conexão não é realizada de forma direta. Todo sistema conectado por uma NoC necessita de interfaces de rede (NIs) para intermediar a conexão dos elementos de processamento aos roteadores da rede. O objetivo desse trabalho é apresentar soluções arquiteturais de interfaces de rede para NoCs que atendam diferentes aplicações de forma genérica. Neste trabalho foram desenvolvidas interfaces de redes reutilizáveis e parametrizáveis, e para atender a estas características, as interfaces de rede possibilitam a configuração de diversos parâmetros arquiteturais, como largura da palavra de dados dos EPs, profundidade das FIFOs das interfaces, profundidade das FIFOs da NoC e largura de dados da rede, possibilitando prover a interconexão de qualquer aplicação com um mínimo de reprojeto. As interfaces de rede, juntamente com a NoC, são responsáveis pelo desempenho da comunicação da aplicação e, para isso, o projeto de uma NI deve ser capaz de atender aos requisitos do sistema, por isso, a importância de se obter um projeto de NIs flexível. Para validar as arquiteturas das NIs desenvolvidas, os módulos do decodificador de vídeo no contexto do padrão H.264 foram conectados à NoC através das interfaces projetadas. A partir dessa implementação, puderam-se levantar diversas necessidades que devem ser atendidas pelas NIs. Por fim, foram analisados os resultados de síntese das NIs para diferentes configurações. Também foram verificados os resultados de síntese e desempenho do decodificador de vídeo H.264 conectado pelas NIs à NoC. Com relação aos resultados de síntese em FPGA, a implementação do decodificador de vídeo com NoC e NIs não apresentou um grande aumento em área quando comparada a implementação com conexão ponto-a-ponto. Além disso, para diferentes configurações das NIs, a NoC pode ser utilizada atendendo aos requisitos de desempenho exigidos pela aplicação, sem a necessidade de operar na sua máxima taxa de operação para a resolução QCIF. / Networks-on-Chip (NoCs) have emerged as an alternative to the current interconnection problems arising from the scaling technology for manufacturing integrated circuits. The development of transistors with nanometer-wide has enabled the integration of highly complex systems on a single silicon wafer. Thus, SoCs (Systemson- Chip) have integrated numerous processing elements (EPs) and NoCs have been presented as an effective option in providing the interconnection of these elements, allowing scalability and parallelism to the system. However, this connection is not done directly. Every system connected by NoC needs network interfaces to intermediate the connection of processing elements to network routers. The goal of this thesis is to present architectural solutions for network interfaces for applications in general. In this work we developed a generic, reusable and configurable network interface. The proposed network interface enables the configuration of several architectural parameters, such as data width of the packets, FIFOs depth of the interfaces, FIFO depth and data width of the NoC, and thus, being able to provide the interconnection of any application with a minimal redesign. Network interfaces, together with the NoC, are responsible for application performance and, therefore, the design of an NI should be able to support the system requirements. To validate the architecture of developed NI, the modules of H.264 decoder were connected to NoC through designed interface. From this implementation, one could raise several needs that must be supported by the NIs. Finally, we analyzed the results of synthesis of the NIs for different configurations. It was also analyzed the results of synthesis and performance of H.264 video decoder connected by NIs to NoC. According to results for FPGA synthesis, the implementation of video decoder with NoC and NIs did not show a large increase in area when compared with the implementation of peer-to-peer. Moreover, for different configurations, the NoC can be used according to time requisitions required by the application, without the need to operate at its maximum operation frequency for QCIF resolution.

Les applications de traitement d'image et vidéo sont caractérisées par le traitement d'une grande quantité de données. La conception de ces applications complexes avec des méthodologies de conception traditionnelles bas niveau provoque 1'augmentation des coûts de développement. Afin de résoudre ces défis, des outils de synthèse haut niveau ont été proposés. Le principe de base est de modéliser le comportement de l'ensemble du système en utilisant des spécifications haut niveau afin de permettre la synthèse automatique vers des spécifications bas niveau pour implémentation efficace en FPGA. Cependant, l'inconvénient principal de ces outils de synthèse haut niveau est le manque de prise en compte de la totalité du système, c.-à-d. la création de la communication entre les différents composants pour atteindre le niveau système n'est pas considérée. Le but de cette thèse est d'élever le niveau d'abstraction dans la conception des systèmes embarqués au niveau système. Nous proposons un flot de conception qui permet une synthèse matérielle efficace des applications de traitement vidéo décrites en utilisant un langage spécifique à un domaine pour la programmation flot-de- données. Le flot de conception combine un compilateur flot- de-données pour générer des descriptions à base de code C et d'un synthétiseur pour générer des descriptions niveau de transfert de registre. Le défi majeur de l'implémentation en FPGA des canaux de communication des programmes flot-de-données basés sur un modèle de calcul est la minimisation des frais généraux de la communication. Pour cela, nous avons introduit une nouvelle approche de synthèse de l'interface qui mappe les grandes quantités des données vidéo, à travers des m'mémoires partagées sur FPGA. Ce qui conduit à une diminution considérable de la latence et une augmentation du débit. Ces résultats ont été démontrés sur la synthèse matérielle du standard vidéo émergent High-Efficiency Video Coding (HEVC). / Image and video processing applications are characterized by the processing of a huge amount of data. The design of such complex applications with traditional design methodologies at lowlevel of abstraction causes increasing development costs. In order to resolve the above mentioned challenges, Electronic System Level (ESL) synthesis or High-Level Synthesis (HLS) tools were proposed. The basic premise is to model the behavior of the entire system using high level specifications, and to enable the automatic synthesis to low-level specifications for efficient implementation in Field-Programmable Gate array (FPGA). However, the main downside of the HLS tools is the lack of the entire system consideration, i.e. the establishment of the communications between these components to achieve the system-level is not yet considered. The purpose of this thesis is to raise the level of abstraction in the design of embedded systems to the system-level. A novel design flow was proposed that enables an efficient hardware implementation of video processing applications described using a Domain Specific Language (DSL) for dataflow programming. The design flow combines a dataflow compiler for generating C-based HLS descriptions from a dataflow description and a C-to-gate synthesizer for generating Register-Transfer Level (RTL) descriptions. The challenge of implementing the communication channels of dataflow programs relying on Model of Computation (MoC) in FPGA is the minimization of the communication overhead. In this issue, we introduced a new interface synthesis approach that maps the large amounts of data that multimedia and image processing applications process, to shared memories on the FPGA. This leads to a tremendous decrease in the latency and an increase in the throughput. These results were demonstrated upon the hardware synthesis of the emerging High-Efficiency Video Coding (HEVC) standard.

<p>The progression of technical development has yielded practicable camera systems for the acquisition of so called depth maps, images with depth information. </p><p>Images and movies with depth information open the door for new types of applications in the area of computer graphics and vision. That implies that they will need to be processed in all increasing volumes.</p><p>Increased depth image processing puts forth the demand for a standardized data format for the exchange of image data with depth information, both still and animated. Software to convert acquired depth data to such videoformats is highly necessary. </p><p>This diploma thesis sheds light on many of the issues that come with this new task group. It spans from data acquisition over readily available software for the data encoding to possible future applications. </p><p>Further, a software architecture fulfilling all of the mentioned demands is presented. </p><p>The encoder is comprised of a collection of UNIX programs that generate MPEG Z/Alpha, an MPEG2 based video format. MPEG Z/Alpha contains beside MPEG2's standard data streams one extra data stream to store image depth information (and transparency). </p><p>The decoder suite, called TexMPEG, is a C library for the in-memory decompression of MPEG Z/Alpha. Much effort has been put into video decoder parallelization, and TexMPEG is now capable of decoding multiple video streams, not only in parallel internally, but also with inherent frame synchronization between parallely decoded MPEG videos.</p>

The progression of technical development has yielded practicable camera systems for the acquisition of so called depth maps, images with depth information. Images and movies with depth information open the door for new types of applications in the area of computer graphics and vision. That implies that they will need to be processed in all increasing volumes. Increased depth image processing puts forth the demand for a standardized data format for the exchange of image data with depth information, both still and animated. Software to convert acquired depth data to such videoformats is highly necessary. This diploma thesis sheds light on many of the issues that come with this new task group. It spans from data acquisition over readily available software for the data encoding to possible future applications. Further, a software architecture fulfilling all of the mentioned demands is presented. The encoder is comprised of a collection of UNIX programs that generate MPEG Z/Alpha, an MPEG2 based video format. MPEG Z/Alpha contains beside MPEG2's standard data streams one extra data stream to store image depth information (and transparency). The decoder suite, called TexMPEG, is a C library for the in-memory decompression of MPEG Z/Alpha. Much effort has been put into video decoder parallelization, and TexMPEG is now capable of decoding multiple video streams, not only in parallel internally, but also with inherent frame synchronization between parallely decoded MPEG videos.