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1	Akcelerace HDR tone-mappingu na platformě Xilinx Zynq / HDR Tone-Mapping Acceleration on Xilinx Zynq Platform Nosko, Svetozár January 2016 (has links) This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
2	Evaluating Vivado High-Level Synthesis on OpenCV Functions for the Zynq-7000 FPGA Johansson, Henrik January 2015 (has links) More complex and intricate Computer Vision algorithms combined with higher resolution image streams put bigger and bigger demands on processing power. CPU clock frequencies are now pushing the limits of possible speeds, and have instead started growing in number of cores. Most Computer Vision algorithms' performance respond well to parallel solutions. Dividing the algorithm over 4-8 CPU cores can give a good speed-up, but using chips with Programmable Logic (PL) such as FPGA's can give even more. An interesting recent addition to the FPGA family is a System on Chip (SoC) that combines a CPU and an FPGA in one chip, such as the Zynq-7000 series from Xilinx. This tight integration between the Programmable Logic and Processing System (PS) opens up for designs where C programs can use the programmable logic to accelerate selected parts of the algorithm, while still behaving like a C program. On that subject, Xilinx has introduced a new High-Level Synthesis Tool (HLST) called Vivado HLS, which has the power to accelerate C code by synthesizing it to Hardware Description Language (HDL) code. This potentially bridges two otherwise very separate worlds; the ever popular OpenCV library and FPGAs. This thesis will focus on evaluating Vivado HLS from Xilinx primarily with image processing in mind for potential use on GIMME-2; a system with a Zynq-7020 SoC and two high resolution image sensors, tailored for stereo vision. FPGA OpenCV Zynq-7000 Vivado HLS Vivado High Level Synthesis HLS Computer Vision Xilinx System on Chip SoC GIMME-2 Stereo Vision Harris Robotics Robotteknik och automation Computer Engineering Datorteknik

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Akcelerace HDR tone-mappingu na platformě Xilinx Zynq / HDR Tone-Mapping Acceleration on Xilinx Zynq Platform

Evaluating Vivado High-Level Synthesis on OpenCV Functions for the Zynq-7000 FPGA