Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor networks have a wide variety of applications in medical monitoring, environmental sensing and military surveillance. Due to the large number of sensor nodes that may be deployed and the required long system lifetimes, replacing the battery is not an option. Sensor systems must utilize the minimal possible energy while operating over a wide range of operating scenarios. The most of the efforts in the energy management in sensor networks have concentrated on minimizing energy consumption in the communication subsystem. Some researchers have also dealt with the issue of minimizing the energy in computing subsystem of a sensor network node. Some proposals using energy aware software have also been made. Relatively little work has been done on compiler controlled energy management in sensor networks. In this thesis, we present our investigations on how compiler techniques can be used to minimize CPU energy consumption in sensor network nodes. One effectively used energy management technique in general purpose processors, is dynamic voltage scaling. In this thesis we implement and evaluate a compiler assisted DVS algorithm and show its usefulness for a small sensor node processor. We were able to achieve an energy saving of 29% with a little performance slowdown. Scratchpad memories have been widely used for improving performance. In this thesis we show that if the scratchpad size for the system is chosen carefully, then large energy savings can be achieved by using a compiler assisted scratchpad allocation policy. With a small size of 512 byte scratchpad memory we were able to achieve 50% of energy savings. We also studied the behavior of dynamic voltage scaling in presence of scratchpad memory. Our results show that in presence of scratchpad memory less opportunities are found for applying dynamic voltage scaling techniques. The sensor network community lacks a comprehensive benchmark suite, for our study we also implemented a set of applications, representative of computational workload on sensor network nodes. The techniques studied in this thesis can easily be integrated with existing energy management techniques in sensor networks, yielding in additional energy savings.

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This term project deals with the problem of scheduling real-time tasks in overload conditions and techniques for lowering power consumption. Each of these parts features mechanisms and reasons for their using. There are also described specific algorithms, that are implemented, in operating system uC/OS-II, and compared in next phase of master's thesis.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-08-22T17:30:17Z No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-08-23T12:09:32Z (GMT) No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Made available in DSpace on 2018-08-23T13:31:43Z (GMT). No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) Previous issue date: 2018-03-09 / A demanda sem precedentes por poderosos dispositivos de processamento gerou quebras consecutivas de paradigma de projeto de circuito na ?rea de Circuitos Integrados (CIs). O uso de tecnologia submicrom?trica profunda aumenta a densidade de integra??o a n?veis nunca vistos antes. No entanto, com CIs mais densos, a inclina??o do rel?gio e outros efeitos requerem compensa??es em design s?ncrono, o que pode aumentar a ?rea e o consumo de energia a valores inaceit?veis. Como alternativa, o paradigma ass?ncrono est? re-emergindo, focado na efici?ncia de energia. Entre os modelos cl?ssicos de projeto ass?ncrono, o Empacotamento-de-Dados (ED) se destaca pela sua capacidade de fornecer alto desempenho, reduzir a pot?ncia e obter resultados de ?rea semelhante ? dos modelos s?ncronos. Diferentemente dos modelos mais robustos de quase-atraso insens?vel, uma outra classe comum de modelos para implementar circuitos ass?ncronos, circuitos ED requerem o uso extensivo de Elementos de Atraso (EAs) para garantir a correta funcionalidade. No entanto, todos os circuitos s?o afetados por varia??es de Processo, Tens?o e Temperatura (PTT), incluindo a L?gica Combinacional (LC) em ED impondo margem em elementos de atraso. Al?m disso, projetos atuais usam escalonamento de tens?o para melhorar a efici?ncia de energia, o que afeta o atraso diferentemente em LCs e EAs adicionando mais margem em EAs. Um novo modelo baseado em ED chamado Blade usa o conceito de resili?ncia como uma esperan?a para evitar a margem de atraso causada por PTT e escalonamento de tens?o. Contudo, o uso de dois elementos de atraso ir? representar mais margens e mais tempo de teste no circuito final. Assim, este trabalho mostra uma an?lise do comportamento de elementos de atraso sob escalonamento de tens?o e o impacto em testes p?s-sil?cio. Ele introduz um novo termo para determinar o impacto da escala de tens?o sobre os elementos de atraso e tamb?m a compara??o entre os EAs mais utilizados em projetos ED usando esta nova m?trica. Uma an?lise de testes em modelos ED e Blade ? apresentada e o impacto da escala de tens?o nestes projetos ? analisado. Finalmente, um novo elemento de atraso ? proposto focando na redu??o de margem e redu??o no tempo de teste para o modelo Blade. / The unprecedented demand for powerful processing devices has generated consecutive circuit design paradigm breaks in the Integrated Circuits (ICs) arena. The use of deep submicron technology increases the integration density to levels never seen before. However, with denser ICs, clock skew and other effects require compensations in synchronous design, which can increase area overhead and power consumption to unacceptable values. As an alternative, the asynchronous paradigm is re-emerging, focused on power efficiency. Among classical asynchronous design templates, the Bundled-Data (BD) one stands off for its capability to provide high performance, reduce power and achieve area results similar to that of synchronous designs. Unlike the more robust Quasi-Delay Insensitive (QDI) templates, another common class of templates to implement asynchronous circuits, BD circuits require the extensive use of Delay Elements (DEs) to guarantee correct functionality. However, all circuits are affected by Process, Voltage and Temperature (PVT) variations, including the Combinational Logic (CL) on BD imposing margin on delay elements. In addition, current designs use voltage scaling to improve power efficiency, which impacts the delay differently in CLs and DEs adding more margin in DEs. A new template based on BD called Blade uses resiliency concept as a hope to avoid the delay margin caused by PVT and voltage scaling. Although, the use of two delay elements will represents more margins and extra test time on final circuit. So, this work shows an analysis of delay elements behavior under voltage scaling and the impact on post-silicon tests. It introduces a new term to determine the voltage scaling impact on delay elements and also the comparison between the most used DEs on BD designs using this novel metric. An analysis of tests in BD and Blade templates are presented and the impact of voltage scaling in these designs is analyzed. Finally, a novel delay element is proposed focusing in margin reduction and reduction in test time for Blade template.