Chung, Wai Fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / 摘要 --- p.III / ACKNOWLEDGEMENT --- p.IV / CONTENTS --- p.V / LIST OF FIGURES --- p.VIII / LIST OF TABLES --- p.X / LIST OF TABLES --- p.X / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Receiver Architecture --- p.3 / Chapter 1.2.1 --- Zero-IF Receivers --- p.4 / Chapter 1.2.2 --- Low-IF Receivers --- p.6 / Chapter 1.2.2.1 --- Hartley Architecture --- p.7 / Chapter 1.2.2.2 --- Weaver Architecture --- p.9 / Chapter 1.3 --- Image-rejection ratio --- p.10 / Chapter 1.4 --- Thesis Organization --- p.12 / Chapter CHAPTER 2 --- FUNDAMENTALS OF OSCILLATOR --- p.13 / Chapter 2.1 --- Basic Oscillator Theory --- p.13 / Chapter 2.2 --- Varactor --- p.15 / Chapter 2.3 --- Inductor --- p.17 / Chapter 2.4 --- Phase noise --- p.22 / Chapter 2.4.1 --- The Leeson ´ةs phase noise expression --- p.24 / Chapter 2.4.2 --- Linear model --- p.25 / Chapter 2.4.3 --- Linear Time-Variant phase noise model --- p.28 / Chapter CHAPTER 3 --- FULLY-INTEGRATED CMOS OSCILLATOR DESIGN --- p.31 / Chapter 3.1 --- Ring oscillator --- p.31 / Chapter 3.2 --- LC oscillator --- p.33 / Chapter 3.2.1 --- LC-tank resonator --- p.34 / Chapter 3.2.2 --- Negative transconductance --- p.36 / Chapter 3.3 --- Generation of quadrature phase signals --- p.39 / Chapter 3.4 --- Quadrature VCO topologies --- p.41 / Chapter 3.4.1 --- Parallel-coupled QVCO --- p.41 / Chapter 3.4.2 --- Series-coupled QVCO --- p.46 / Chapter 3.4.3 --- QVCO with Back-gate Coupling --- p.47 / Chapter 3.4.4 --- QVCO using superharmonic coupling --- p.49 / Chapter 3.5 --- Novel QVCO using back-gate superharmonic coupling --- p.52 / Chapter 3.5.1 --- Tuning range --- p.54 / Chapter 3.5.2 --- Negative gm --- p.55 / Chapter 3.5.3 --- Phase noise calculation --- p.56 / Chapter 3.5.4 --- Coupling coefficient --- p.57 / Chapter 3.5.5 --- Low-voltage and low-power design --- p.59 / Chapter 3.5.6 --- Layout Consideration --- p.61 / Chapter 3.5.6.1 --- Symmetrical Layout and parasitics --- p.61 / Chapter 3.5.6.2 --- Metal width and number of vias --- p.63 / Chapter 3.5.6.3 --- Substrate contact and guard ring --- p.63 / Chapter 3.5.7 --- Simulation Results --- p.65 / Chapter 3.5.7.1 --- Frequency and output power --- p.65 / Chapter 3.5.7.2 --- Quadrature signal generation --- p.67 / Chapter 3.5.7.3 --- Tuning range --- p.67 / Chapter 3.5.7.4 --- Power consumption --- p.68 / Chapter 3.5.7.5 --- Phase noise --- p.69 / Chapter 3.6 --- Polyphase filter and Single-sideband mixer design --- p.70 / Chapter 3.6.1 --- Polyphase filter --- p.72 / Chapter 3.6.2 --- Layout Consideration --- p.74 / Chapter 3.6.3 --- Simulation results --- p.76 / Chapter 3.7 --- Comparison with parallel-coupled QVCO --- p.78 / Chapter CHAPTER 4 --- EXPERIMENTAL RESULTS --- p.80 / Chapter 4.1 --- Test Fixture --- p.82 / Chapter 4.2 --- Measurement set-up --- p.84 / Chapter 4.3 --- Measurement results --- p.86 / Chapter 4.3.1 --- Proposed QVCO using back-gate superharmonic coupling --- p.86 / Chapter 4.3.1.1 --- Output Spectrum --- p.86 / Chapter 4.3.1.2 --- Tuning range --- p.87 / Chapter 4.3.1.3 --- Phase noise --- p.88 / Chapter 4.3.1.4 --- Power consumption --- p.88 / Chapter 4.3.1.5 --- Image-rejection ratio --- p.89 / Chapter 4.3.2 --- Parallel-coupled QVCO --- p.90 / Chapter 4.3.2.1 --- Output spectrum --- p.90 / Chapter 4.3.2.2 --- Power consumption --- p.90 / Chapter 4.3.2.3 --- Tuning range --- p.91 / Chapter 4.3.2.4 --- Phase noise --- p.92 / Chapter 4.3.3 --- Comparison between proposed and parallel-coupled QVCO --- p.93 / Chapter CHAPTER 5 --- CONCLUSIONS --- p.95 / Chapter 5.1 --- Conclusions --- p.95 / Chapter 5.2 --- Future work --- p.97 / REFERENCES --- p.98

Thesis (M.S. in electrical engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 55-56).

Thesis (MScIng)--University of Stellenbosch, 2008. / Bibliography. Also available via the Internet.

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 93-97). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2005. / Printout. Includes bibliographical references (leaves 90-91). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 31-32). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 57-58). Also available on the World Wide Web.

This thesis presents algorithms and tools for the automated design of RF LC CMOS voltage controlled oscillators (VCOs) with low phase noise given a set of specifications. The electromagnetic solver, ASITIC, combined with the circuit simulator, SpectreRF, allows optimization of the VCO circuit parameters and inductor layout. This approach gives a phase noise improvement of up to 20 dBc/Hz in the flicker noise region and up to 5 dBc/Hz in the thermal noise region. An optimization program for the computer-aided design of on-chip spiral inductors has also been developed. This program allows the designer to obtain the layout of an inductor with a required inductance value and maximal quality factor, thus enabling a reduction in the phase noise of the VCO being designed. The circuit simulator SPICE3 has been extended to handle phase noise analysis based on a non-linear perturbation analysis for oscillators. The implemented technique allows for an accurate simulation of phase noise due to devices described either by analytical or numerical models. With this extension, the automated design of RF LC oscillators can be performed within the SPICE3 framework. Furthermore, the technique is available in a public domain software and can be extended to other application domains. / Graduation date: 2004

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / M/A-COM, Inc. has developed a highly integrated transmitter chip set for wireless telemetry applications under a U.S. Army Development Contract. The chip set is comprised of a voltage controlled oscillator (VCO), a silicon synthesizer/phase locked loop (PLL), and a family of power amplifiers (PA's). The chip-set is designed to operate over the military L and S Band frequencies as well as the lower commercial ISM band. Using these components, M/A-COM has produced IRIG compliant transmitter modules for ballistic telemetry applications. These modules have been successfully flight tested by the Army Research Laboratory at Aberdeen Proving Ground, Maryland. This paper reviews the transmitter system architecture and presents test data for the transmitter module and individual components.