No description available.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted. A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region. The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell. Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.

Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009. / Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.

Η χρήση ταλαντωτών γίνεται σε όλα τα τηλεπικοινωνιακά και στα περισσότερα ψηφιακά κυκλώματα. Αποτελεί βασικό πυλώνα πάνω στον οποίο στηρίζεται η ποιότητα του τηλεπικοινωνιακού σήματος. Για να παράγει έξοδο για διαφορετικά κανάλια μιας τηλεπικοινωνιακής περιοχής, θα πρέπει ο ταλαντωτής μας να αλλάζει την παραγόμενη συχνότητα του. Μια ειδική κατηγορία αυτών είναι οι ταλαντωτές ελεγχόμενοι από τάση, VCO . Οι ταλαντωτές που χρησιμοποιούνται σήμερα ανήκουν σε 2 βασικές κατηγορίες: ● Ταλαντωτές LC, όπου χρησιμοποιείται ένα συντονιζόμενο κύκλωμα, αποτελούμενο από επαγωγή L και χωρητικότητα C, που από κοινού καθορίζουν την συχνότητα λειτουργίας του ταλαντωτή. ● Ταλαντωτές δακτυλίου, χρησιμοποιούν κυκλώματα RC μετάθεσης φάσης Οι πρώτοι υπερέχουν στον χαμηλότερο θόρυβο και κατανάλωση, οι δεύτεροι σε μικρότερη επιφάνεια υλοποίησης και μεγαλύτερη περιοχή συχνοτήτων. Η μελέτη έγινε για ολοκληρωμένο κύκλωμα ASIC, BiCmos 0,35μm της Austriamicrosystems. Η περιοχή συχνοτήτων του VCO είναι 10GHz – 10,5GHz. Η πορεία πέρασε από την εξομοίωση των επιμέρους τμημάτων του ταλαντωτή και σταδιακά στην σύνθεσή τους. Το ζητούμενο ήταν να επιτευχθεί η χαμηλότερη στάθμη θορύβου, στα προδιαγεγραμμένα όρια λειτουργίας. Το γεγονός αυτό οδήγησε σε διαρκείς εξομοιώσεις. Στην συνέχεια μετεξελίχθηκε σε ορθογώνιο ταλαντωτή QVCO με την ίδια περιοχή εξόδου. Η διαδικασία επαναλήφτηκε για την επίτευξη της μέγιστης απόδοσης. Για την εξομοίωση χρησιμοποιήθηκε το Advanced Design System της Agilent. Η τροφοδοσία του κυκλώματος είναι στα 3volts. Η κατανάλωση 42mw για τον ταλαντωτή VCO, 90mW για τον ταλαντωτή QVCO. Ο θόρυβος φάσης είναι χαμηλότερος από -114dBc/Hz στα 10KHz για το VCO και -100dBc/Hz στα 10KHz για το QVCO. / Design of an integrated ASIC Austriamicrosystems (AMS), 0.35mm technology, quadrature voltage controlled oscillator in the range of 10GHz. The design and simulation environment had occurred in the ADS of Agilent. This design was aimed at the lowest possible noise level.

No description available.

No description available.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

Indiana University-Purdue University Indianapolis (IUPUI) / A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.