Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 65-69).

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Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted. A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region. The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell. Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.

Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy. The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.